base/traceflags.py: Add new commit rate trace flag. build/SConstruct: Add extra option for efence. cpu/beta_cpu/alpha_full_cpu_impl.hh: Use function calls instead of direct indexing (avoids confusion). cpu/beta_cpu/commit_impl.hh: Add commit rate trace output (might not be worthwhile in the future). cpu/beta_cpu/decode_impl.hh: Remove some older hacks. Fix it so that the isntruction properly sets its next PC to the one calculated by the branch. cpu/beta_cpu/fetch_impl.hh: Remove old commented code. cpu/beta_cpu/iew_impl.hh: Add extra check to ensure that the instruction is valid. cpu/beta_cpu/regfile.hh: Include trace file. --HG-- extra : convert_revision : 4ee1dc88f8a5ed9b65486c6c111a3718a8040e42
509 lines
17 KiB
C++
509 lines
17 KiB
C++
// @todo: Bug when something reaches execute, and mispredicts, but is never
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// put into the ROB because the ROB is full. Need rename stage to predict
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// the free ROB entries better.
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#ifndef __COMMIT_IMPL_HH__
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#define __COMMIT_IMPL_HH__
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#include "base/timebuf.hh"
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#include "cpu/beta_cpu/commit.hh"
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#include "cpu/exetrace.hh"
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template <class Impl>
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SimpleCommit<Impl>::SimpleCommit(Params ¶ms)
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: dcacheInterface(params.dcacheInterface),
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iewToCommitDelay(params.iewToCommitDelay),
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renameToROBDelay(params.renameToROBDelay),
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renameWidth(params.renameWidth),
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iewWidth(params.executeWidth),
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commitWidth(params.commitWidth)
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{
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_status = Idle;
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::regStats()
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{
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commitCommittedInsts
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.name(name() + ".commitCommittedInsts")
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.desc("The number of committed instructions")
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.prereq(commitCommittedInsts);
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commitSquashedInsts
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.name(name() + ".commitSquashedInsts")
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.desc("The number of squashed insts skipped by commit")
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.prereq(commitSquashedInsts);
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commitSquashEvents
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.name(name() + ".commitSquashEvents")
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.desc("The number of times commit is told to squash")
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.prereq(commitSquashEvents);
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commitNonSpecStalls
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.name(name() + ".commitNonSpecStalls")
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.desc("The number of times commit has been forced to stall to "
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"communicate backwards")
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.prereq(commitNonSpecStalls);
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commitCommittedBranches
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.name(name() + ".commitCommittedBranches")
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.desc("The number of committed branches")
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.prereq(commitCommittedBranches);
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commitCommittedLoads
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.name(name() + ".commitCommittedLoads")
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.desc("The number of committed loads")
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.prereq(commitCommittedLoads);
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commitCommittedMemRefs
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.name(name() + ".commitCommittedMemRefs")
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.desc("The number of committed memory references")
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.prereq(commitCommittedMemRefs);
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branchMispredicts
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.name(name() + ".branchMispredicts")
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.desc("The number of times a branch was mispredicted")
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.prereq(branchMispredicts);
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n_committed_dist
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.init(0,commitWidth,1)
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.name(name() + ".COM:committed_per_cycle")
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.desc("Number of insts commited each cycle")
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.flags(Stats::pdf)
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;
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
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{
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DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
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cpu = cpu_ptr;
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
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{
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DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
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timeBuffer = tb_ptr;
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// Setup wire to send information back to IEW.
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toIEW = timeBuffer->getWire(0);
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// Setup wire to read data from IEW (for the ROB).
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robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
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{
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DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
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renameQueue = rq_ptr;
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// Setup wire to get instructions from rename (for the ROB).
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fromRename = renameQueue->getWire(-renameToROBDelay);
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
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{
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DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
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iewQueue = iq_ptr;
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// Setup wire to get instructions from IEW.
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fromIEW = iewQueue->getWire(-iewToCommitDelay);
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::setROB(ROB *rob_ptr)
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{
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DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
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rob = rob_ptr;
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::tick()
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{
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// If the ROB is currently in its squash sequence, then continue
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// to squash. In this case, commit does not do anything. Otherwise
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// run commit.
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if (_status == ROBSquashing) {
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if (rob->isDoneSquashing()) {
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_status = Running;
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} else {
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rob->doSquash();
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// Send back sequence number of tail of ROB, so other stages
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// can squash younger instructions. Note that really the only
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// stage that this is important for is the IEW stage; other
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// stages can just clear all their state as long as selective
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// replay isn't used.
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toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
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toIEW->commitInfo.robSquashing = true;
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}
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} else {
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commit();
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}
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markCompletedInsts();
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// Writeback number of free ROB entries here.
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DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
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rob->numFreeEntries());
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toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::commit()
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{
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//////////////////////////////////////
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// Check for interrupts
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//////////////////////////////////////
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// Process interrupts if interrupts are enabled and not in PAL mode.
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// Take the PC from commit and write it to the IPR, then squash. The
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// interrupt completing will take care of restoring the PC from that value
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// in the IPR. Look at IPR[EXC_ADDR];
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// hwrei() is what resets the PC to the place where instruction execution
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// beings again.
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#ifdef FULL_SYSTEM
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if (ISA::check_interrupts &&
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cpu->check_interrupts() &&
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!xc->inPalMode()) {
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// Will need to squash all instructions currently in flight and have
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// the interrupt handler restart at the last non-committed inst.
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// Most of that can be handled through the trap() function. The
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// processInterrupts() function really just checks for interrupts
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// and then calls trap() if there is an interrupt present.
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// CPU will handle implementation of the interrupt.
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cpu->processInterrupts();
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}
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#endif // FULL_SYSTEM
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////////////////////////////////////
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// Check for squash signal, handle that first
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////////////////////////////////////
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// Want to mainly check if the IEW stage is telling the ROB to squash.
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// Should I also check if the commit stage is telling the ROB to squah?
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// This might be necessary to keep the same timing between the IQ and
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// the ROB...
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if (fromIEW->squash) {
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DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
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_status = ROBSquashing;
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InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
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rob->squash(squashed_inst);
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// Send back the sequence number of the squashed instruction.
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toIEW->commitInfo.doneSeqNum = squashed_inst;
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// Send back the squash signal to tell stages that they should squash.
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toIEW->commitInfo.squash = true;
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// Send back the rob squashing signal so other stages know that the
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// ROB is in the process of squashing.
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toIEW->commitInfo.robSquashing = true;
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toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
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toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
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toIEW->commitInfo.nextPC = fromIEW->nextPC;
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toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
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toIEW->commitInfo.globalHist = fromIEW->globalHist;
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if (toIEW->commitInfo.branchMispredict) {
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++branchMispredicts;
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}
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}
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if (_status != ROBSquashing) {
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// If we're not currently squashing, then get instructions.
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getInsts();
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// Try to commit any instructions.
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commitInsts();
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}
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// If the ROB is empty, we can set this stage to idle. Use this
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// in the future when the Idle status will actually be utilized.
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#if 0
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if (rob->isEmpty()) {
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DPRINTF(Commit, "Commit: ROB is empty. Status changed to idle.\n");
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_status = Idle;
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// Schedule an event so that commit will actually wake up
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// once something gets put in the ROB.
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}
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#endif
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}
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// Loop that goes through as many instructions in the ROB as possible and
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// tries to commit them. The actual work for committing is done by the
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// commitHead() function.
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template <class Impl>
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void
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SimpleCommit<Impl>::commitInsts()
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{
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////////////////////////////////////
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// Handle commit
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// Note that commit will be handled prior to the ROB so that the ROB
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// only tries to commit instructions it has in this current cycle, and
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// not instructions it is writing in during this cycle.
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// Can't commit and squash things at the same time...
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////////////////////////////////////
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DynInstPtr head_inst = rob->readHeadInst();
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unsigned num_committed = 0;
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// Commit as many instructions as possible until the commit bandwidth
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// limit is reached, or it becomes impossible to commit any more.
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while (!rob->isEmpty() &&
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head_inst->readyToCommit() &&
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num_committed < commitWidth)
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{
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DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
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// If the head instruction is squashed, it is ready to retire at any
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// time. However, we need to avoid updating any other state
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// incorrectly if it's already been squashed.
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if (head_inst->isSquashed()) {
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// Hack to avoid the instruction being retired (and deleted) if
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// it hasn't been through the IEW stage yet.
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if (!head_inst->isExecuted()) {
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break;
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}
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DPRINTF(Commit, "Commit: Retiring squashed instruction from "
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"ROB.\n");
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// Tell ROB to retire head instruction. This retires the head
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// inst in the ROB without affecting any other stages.
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rob->retireHead();
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++commitSquashedInsts;
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} else {
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// Increment the total number of non-speculative instructions
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// executed.
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// Hack for now: it really shouldn't happen until after the
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// commit is deemed to be successful, but this count is needed
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// for syscalls.
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cpu->funcExeInst++;
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// Try to commit the head instruction.
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bool commit_success = commitHead(head_inst, num_committed);
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// Update what instruction we are looking at if the commit worked.
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if (commit_success) {
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++num_committed;
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// Send back which instruction has been committed.
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// @todo: Update this later when a wider pipeline is used.
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// Hmm, can't really give a pointer here...perhaps the
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// sequence number instead (copy).
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toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
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++commitCommittedInsts;
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if (!head_inst->isNop()) {
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cpu->instDone();
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}
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} else {
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break;
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}
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}
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// Update the pointer to read the next instruction in the ROB.
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head_inst = rob->readHeadInst();
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}
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DPRINTF(CommitRate, "%i\n", num_committed);
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n_committed_dist.sample(num_committed);
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}
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template <class Impl>
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bool
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SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
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{
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// Make sure instruction is valid
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assert(head_inst);
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// If the instruction is not executed yet, then it is a non-speculative
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// or store inst. Signal backwards that it should be executed.
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if (!head_inst->isExecuted()) {
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// Keep this number correct. We have not yet actually executed
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// and committed this instruction.
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cpu->funcExeInst--;
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if (head_inst->isStore() || head_inst->isNonSpeculative()) {
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DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
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"instruction at the head of the ROB, PC %#x.\n",
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head_inst->readPC());
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toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
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// Change the instruction so it won't try to commit again until
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// it is executed.
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head_inst->clearCanCommit();
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++commitNonSpecStalls;
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return false;
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} else {
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panic("Commit: Trying to commit un-executed instruction "
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"of unknown type!\n");
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}
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}
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// Now check if it's one of the special trap or barrier or
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// serializing instructions.
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if (head_inst->isThreadSync() ||
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head_inst->isSerializing() ||
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head_inst->isMemBarrier() ||
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head_inst->isWriteBarrier() )
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{
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// Not handled for now. Mem barriers and write barriers are safe
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// to simply let commit as memory accesses only happen once they
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// reach the head of commit. Not sure about the other two.
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panic("Serializing or barrier instructions"
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" are not handled yet.\n");
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}
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// Check if the instruction caused a fault. If so, trap.
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if (head_inst->getFault() != No_Fault) {
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if (!head_inst->isNop()) {
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#ifdef FULL_SYSTEM
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cpu->trap(fault);
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#else // !FULL_SYSTEM
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panic("fault (%d) detected @ PC %08p", head_inst->getFault(),
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head_inst->PC);
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#endif // FULL_SYSTEM
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}
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}
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// Check if we're really ready to commit. If not then return false.
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// I'm pretty sure all instructions should be able to commit if they've
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// reached this far. For now leave this in as a check.
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if(!rob->isHeadReady()) {
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panic("Commit: Unable to commit head instruction!\n");
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return false;
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}
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// If it's a branch, then send back branch prediction update info
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// to the fetch stage.
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// This should be handled in the iew stage if a mispredict happens...
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if (head_inst->isControl()) {
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#if 0
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toIEW->nextPC = head_inst->readPC();
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//Maybe switch over to BTB incorrect.
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toIEW->btbMissed = head_inst->btbMiss();
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toIEW->target = head_inst->nextPC;
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//Maybe also include global history information.
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//This simple version will have no branch prediction however.
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#endif
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++commitCommittedBranches;
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}
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#if 0
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// Check if the instruction has a destination register.
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// If so add the previous physical register of its logical register's
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// destination to the free list through the time buffer.
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for (int i = 0; i < head_inst->numDestRegs(); i++)
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{
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toIEW->commitInfo.freeRegs.push_back(head_inst->prevDestRegIdx(i));
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}
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#endif
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// Explicit communication back to the LDSTQ that a load has been committed
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// and can be removed from the LDSTQ. Stores don't need this because
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// the LDSTQ will already have been told that a store has reached the head
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// of the ROB. Consider including communication if it's a store as well
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// to keep things orthagonal.
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if (head_inst->isMemRef()) {
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++commitCommittedMemRefs;
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if (head_inst->isLoad()) {
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toIEW->commitInfo.commitIsLoad = true;
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++commitCommittedLoads;
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}
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}
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// Now that the instruction is going to be committed, finalize its
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// trace data.
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if (head_inst->traceData) {
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head_inst->traceData->finalize();
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}
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//Finally clear the head ROB entry.
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rob->retireHead();
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// Return true to indicate that we have committed an instruction.
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return true;
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::getInsts()
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{
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//////////////////////////////////////
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// Handle ROB functions
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//////////////////////////////////////
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// Read any issued instructions and place them into the ROB. Do this
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// prior to squashing to avoid having instructions in the ROB that
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// don't get squashed properly.
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int insts_to_process = min((int)renameWidth, fromRename->size);
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for (int inst_num = 0;
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inst_num < insts_to_process;
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++inst_num)
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{
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if (!fromRename->insts[inst_num]->isSquashed()) {
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DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
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fromRename->insts[inst_num]->readPC());
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rob->insertInst(fromRename->insts[inst_num]);
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} else {
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DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
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"squashed, skipping.\n",
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fromRename->insts[inst_num]->seqNum,
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fromRename->insts[inst_num]->readPC());
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}
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}
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}
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template <class Impl>
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void
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SimpleCommit<Impl>::markCompletedInsts()
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{
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// Grab completed insts out of the IEW instruction queue, and mark
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// instructions completed within the ROB.
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for (int inst_num = 0;
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inst_num < iewWidth && fromIEW->insts[inst_num];
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++inst_num)
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{
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DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
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fromIEW->insts[inst_num]->readPC(),
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fromIEW->insts[inst_num]->seqNum);
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// Mark the instruction as ready to commit.
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fromIEW->insts[inst_num]->setCanCommit();
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}
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}
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template <class Impl>
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uint64_t
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SimpleCommit<Impl>::readCommitPC()
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{
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return rob->readHeadPC();
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}
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#endif // __COMMIT_IMPL_HH__
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