563 lines
10 KiB
INI
563 lines
10 KiB
INI
[root]
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type=Root
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children=system
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dummy=0
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[system]
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type=System
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children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
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mem_mode=timing
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physmem=system.physmem
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[system.cpu0]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[0]
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test=system.cpu0.l1c.cpu_side
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[system.cpu0.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu0.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu0.test
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mem_side=system.toL2Bus.port[1]
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[system.cpu0.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu1]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[1]
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test=system.cpu1.l1c.cpu_side
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[system.cpu1.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu1.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu1.test
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mem_side=system.toL2Bus.port[2]
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[system.cpu1.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu2]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[2]
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test=system.cpu2.l1c.cpu_side
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[system.cpu2.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu2.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu2.test
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mem_side=system.toL2Bus.port[3]
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[system.cpu2.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu3]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[3]
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test=system.cpu3.l1c.cpu_side
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[system.cpu3.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu3.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu3.test
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mem_side=system.toL2Bus.port[4]
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[system.cpu3.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu4]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[4]
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test=system.cpu4.l1c.cpu_side
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[system.cpu4.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu4.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu4.test
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mem_side=system.toL2Bus.port[5]
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[system.cpu4.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu5]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[5]
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test=system.cpu5.l1c.cpu_side
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[system.cpu5.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu5.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu5.test
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mem_side=system.toL2Bus.port[6]
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[system.cpu5.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu6]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[6]
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test=system.cpu6.l1c.cpu_side
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[system.cpu6.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu6.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu6.test
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mem_side=system.toL2Bus.port[7]
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[system.cpu6.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.cpu7]
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type=MemTest
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children=l1c
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atomic=false
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max_loads=100000
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memory_size=65536
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percent_dest_unaligned=50
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percent_functional=50
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percent_reads=65
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percent_source_unaligned=50
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percent_uncacheable=10
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progress_interval=10000
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trace_addr=0
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functional=system.funcmem.port[7]
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test=system.cpu7.l1c.cpu_side
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[system.cpu7.l1c]
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type=BaseCache
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children=protocol
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adaptive_compression=false
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assoc=4
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=1000
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lifo=false
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max_miss_count=0
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mshrs=12
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=10000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=system.cpu7.l1c.protocol
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repl=Null
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size=32768
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=8
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.cpu7.test
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mem_side=system.toL2Bus.port[8]
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[system.cpu7.l1c.protocol]
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type=CoherenceProtocol
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do_upgrades=true
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protocol=moesi
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[system.funcmem]
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type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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zero=false
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port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
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[system.l2c]
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type=BaseCache
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adaptive_compression=false
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assoc=8
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block_size=64
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compressed_bus=false
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compression_latency=0
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hash_delay=1
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latency=10000
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lifo=false
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max_miss_count=0
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mshrs=92
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prefetch_access=false
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prefetch_cache_check_push=true
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prefetch_data_accesses_only=false
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prefetch_degree=1
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prefetch_latency=100000
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prefetch_miss=false
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prefetch_past_page=false
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prefetch_policy=none
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prefetch_serial_squash=false
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prefetch_use_cpu_id=true
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prefetcher_size=100
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prioritizeRequests=false
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protocol=Null
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repl=Null
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size=65536
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split=false
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split_size=0
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store_compressed=false
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subblock_size=0
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tgts_per_mshr=16
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trace_addr=0
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two_queue=false
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write_buffers=8
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cpu_side=system.toL2Bus.port[0]
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mem_side=system.membus.port[0]
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[system.membus]
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type=Bus
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block_size=64
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bus_id=0
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clock=2
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responder_set=false
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width=16
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port=system.l2c.mem_side system.physmem.port[0]
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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zero=false
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port=system.membus.port[1]
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[system.toL2Bus]
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type=Bus
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block_size=64
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bus_id=0
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clock=2
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responder_set=false
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width=16
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port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
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