4f430e9ab5
arch/mips/isa/bitfields.isa:
add RS_SRL bitfield ...these must be set to 0 for a SRL instruction
arch/mips/isa/decoder.isa:
Make unimplemented instructions Fail instead of just Warn
Edits to SRA & SRAV instructions
Implement CFC1 instructions
Unaligned Memory Access Support (Maybe Not fully functional yet)
Enforce a more strict decode policy (in terms of different bitfields set to 0 on certain instructions)
arch/mips/isa/formats/branch.isa:
Fix disassembly
arch/mips/isa/formats/int.isa:
Add sign extend Immediate and zero extend Immediate to Int class.
Probably a bit unnecessary in the long run since these manipulations could
be done in the actually instruction instead of keep a int value
arch/mips/isa/formats/mem.isa:
Comment/Remove out split-memory access code... revisit this after SimpleCPU works
arch/mips/isa/formats/unimp.isa:
Add inst2string function to Unimplemented panic. PRints out the instruction
binary to help in debuggin
arch/mips/isa/formats/unknown.isa:
define inst2string function , use in unknown disassembly and panic function
arch/mips/isa/operands.isa:
Make "Mem" default to a unsigned word since this is MIPS32
arch/mips/isa_traits.hh:
change return values to 32 instead of 64
arch/mips/linux_process.cc:
assign some syscalls to the right functions
cpu/static_inst.hh:
more debug functions for MIPS (these will be move to the mips directory soon)
mem/page_table.cc:
mem/page_table.hh:
toward a better implementation for unaligned memory access
mem/request.hh:
NO ALIGN FAULT flag added to support unaligned memory access
sim/syscall_emul.cc:
additional SyscallVerbose comments
--HG--
extra : convert_revision : 1987d80c9f4ede507f1f0148435e0bee97d2428c
131 lines
3.8 KiB
C++
131 lines
3.8 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Definitions of page table.
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*/
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#include <string>
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#include <map>
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#include <fstream>
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#include "arch/faults.hh"
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#include "base/bitfield.hh"
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#include "base/intmath.hh"
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#include "base/trace.hh"
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#include "mem/page_table.hh"
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#include "sim/builder.hh"
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#include "sim/sim_object.hh"
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#include "sim/system.hh"
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using namespace std;
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using namespace TheISA;
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PageTable::PageTable(System *_system, Addr _pageSize)
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: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
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system(_system)
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{
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assert(isPowerOf2(pageSize));
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}
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PageTable::~PageTable()
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{
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}
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Fault
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PageTable::page_check(Addr addr, int size, uint32_t flags) const
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{
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if (size < sizeof(uint64_t)) {
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if (!isPowerOf2(size)) {
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panic("Invalid request size!\n");
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return genMachineCheckFault();
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}
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if (((size - 1) & addr) && (flags & NO_ALIGN_FAULT == 0))
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return genAlignmentFault();
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}
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else {
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if ((addr & (VMPageSize - 1)) + size > VMPageSize) {
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panic("Invalid request size!\n");
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return genMachineCheckFault();
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}
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if (((sizeof(uint64_t) - 1) & addr) && (flags & NO_ALIGN_FAULT == 0))
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return genAlignmentFault();
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}
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return NoFault;
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}
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void
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PageTable::allocate(Addr vaddr, int size)
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{
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// starting address must be page aligned
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assert(pageOffset(vaddr) == 0);
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for (; size > 0; size -= pageSize, vaddr += pageSize) {
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std::map<Addr,Addr>::iterator iter = pTable.find(vaddr);
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if (iter != pTable.end()) {
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// already mapped
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fatal("PageTable::allocate: address 0x%x already mapped", vaddr);
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}
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pTable[vaddr] = system->new_page();
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}
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}
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bool
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PageTable::translate(Addr vaddr, Addr &paddr)
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{
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Addr page_addr = pageAlign(vaddr);
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std::map<Addr,Addr>::iterator iter = pTable.find(page_addr);
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if (iter == pTable.end()) {
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return false;
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}
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paddr = iter->second + pageOffset(vaddr);
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return true;
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}
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Fault
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PageTable::translate(CpuRequestPtr &req)
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{
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assert(pageAlign(req->vaddr + req->size - 1) == pageAlign(req->vaddr));
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if (!translate(req->vaddr, req->paddr)) {
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return genMachineCheckFault();
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}
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return page_check(req->paddr, req->size, req->flags);
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}
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