gem5/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
Andreas Hansson 74553c7d3f stats: Update the stats to reflect bus and memory changes
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00

968 lines
110 KiB
Text

---------- Begin Simulation Statistics ----------
sim_seconds 0.629145 # Number of seconds simulated
sim_ticks 629144850500 # Number of ticks simulated
final_tick 629144850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 104232 # Simulator instruction rate (inst/s)
host_op_rate 141949 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 47369420 # Simulator tick rate (ticks/s)
host_mem_usage 254336 # Number of bytes of host memory used
host_seconds 13281.67 # Real time elapsed on the host
sim_insts 1384370590 # Number of instructions simulated
sim_ops 1885325342 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu.inst 155072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 30241984 # Number of bytes read from this memory
system.physmem.bytes_read::total 30397056 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 155072 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 155072 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 2423 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 472531 # Number of read requests responded to by this memory
system.physmem.num_reads::total 474954 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 246481 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 48068396 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 48314877 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 246481 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 246481 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 6723844 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 6723844 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 6723844 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 246481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 48068396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 55038721 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 474954 # Total number of read requests seen
system.physmem.writeReqs 66098 # Total number of write requests seen
system.physmem.cpureqs 545348 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 30397056 # Total number of bytes read from memory
system.physmem.bytesWritten 4230272 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 30397056 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 4230272 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 163 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4296 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 29873 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 29676 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 29740 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 29705 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 29805 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 29834 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 29631 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 29439 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 29482 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 29490 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 29536 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 29644 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 29703 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 29807 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 29631 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 29795 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 4174 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 4102 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 4138 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 4148 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 4226 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 4225 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 4174 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 4097 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 4098 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 4096 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 4140 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 629144781500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 474954 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 66098 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 407688 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 66635 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 380 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 69 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 17 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2874 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2873 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 173211 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 199.837655 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 132.549683 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 508.405937 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-65 59600 34.41% 34.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-129 42691 24.65% 59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-193 39909 23.04% 82.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-257 25367 14.65% 96.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-321 276 0.16% 96.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-385 104 0.06% 96.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-449 98 0.06% 97.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-513 91 0.05% 97.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-577 88 0.05% 97.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-641 83 0.05% 97.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-705 78 0.05% 97.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-769 81 0.05% 97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-833 73 0.04% 97.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-897 74 0.04% 97.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-961 79 0.05% 97.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1025 80 0.05% 97.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1089 75 0.04% 97.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1153 70 0.04% 97.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1217 80 0.05% 97.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1281 73 0.04% 97.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1345 78 0.05% 97.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1409 73 0.04% 97.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1473 3309 1.91% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1537 4 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1601 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1665 4 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1857 1 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1985 2 0.00% 99.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2049 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2113 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2177 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2241 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2305 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2369 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2433 3 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2497 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2625 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2689 2 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2753 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2817 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3009 1 0.00% 99.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3137 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3457 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3649 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4161 78 0.05% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4225 2 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4289 1 0.00% 99.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4353 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5121 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5377 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8193 558 0.32% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 173211 # Bytes accessed per row activation
system.physmem.totQLat 2060605250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 15116660250 # Sum of mem lat for all requests
system.physmem.totBusLat 2373955000 # Total cycles spent in databus access
system.physmem.totBankLat 10682100000 # Total cycles spent in bank access
system.physmem.avgQLat 4340.03 # Average queueing delay per request
system.physmem.avgBankLat 22498.53 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 31838.56 # Average memory access latency
system.physmem.avgRdBW 48.31 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 6.72 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 48.31 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 6.72 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.43 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.02 # Average read queue length over time
system.physmem.avgWrQLen 17.41 # Average write queue length over time
system.physmem.readRowHits 318020 # Number of row buffer hits during reads
system.physmem.writeRowHits 49639 # Number of row buffer hits during writes
system.physmem.readRowHitRate 66.98 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.10 # Row buffer hit rate for writes
system.physmem.avgGap 1162817.59 # Average gap between requests
system.membus.throughput 55038619 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 408879 # Transaction distribution
system.membus.trans_dist::ReadResp 408878 # Transaction distribution
system.membus.trans_dist::Writeback 66098 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4296 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4296 # Transaction distribution
system.membus.trans_dist::ReadExReq 66075 # Transaction distribution
system.membus.trans_dist::ReadExResp 66075 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side 1024597 # Packet count per connected master and slave (bytes)
system.membus.pkt_count 1024597 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 34627264 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size 34627264 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 34627264 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1206768500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4481136954 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
system.cpu.branchPred.lookups 441633744 # Number of BP lookups
system.cpu.branchPred.condPredicted 353245820 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 30626910 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 253291175 # Number of BTB lookups
system.cpu.branchPred.BTBHits 229518524 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 90.614497 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 52707299 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 2806413 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 0 # DTB read hits
system.cpu.dtb.read_misses 0 # DTB read misses
system.cpu.dtb.write_hits 0 # DTB write hits
system.cpu.dtb.write_misses 0 # DTB write misses
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 0 # DTB read accesses
system.cpu.dtb.write_accesses 0 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 0 # DTB hits
system.cpu.dtb.misses 0 # DTB misses
system.cpu.dtb.accesses 0 # DTB accesses
system.cpu.itb.inst_hits 0 # ITB inst hits
system.cpu.itb.inst_misses 0 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 0 # ITB inst accesses
system.cpu.itb.hits 0 # DTB hits
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 1411 # Number of system calls
system.cpu.numCycles 1258289702 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles 355059035 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 2281679265 # Number of instructions fetch has processed
system.cpu.fetch.Branches 441633744 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 282225823 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 601500993 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 156584245 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 133257591 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 11034 # Number of stall cycles due to pending traps
system.cpu.fetch.IcacheWaitRetryStallCycles 167 # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines 335655020 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 11657170 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1215734936 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.578441 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.176596 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 614278728 50.53% 50.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 43031217 3.54% 54.07% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 96058050 7.90% 61.97% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 55653458 4.58% 66.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 73683625 6.06% 72.61% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 43835223 3.61% 76.21% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 31015132 2.55% 78.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 32844314 2.70% 81.47% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 225335189 18.53% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1215734936 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.350979 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.813318 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 405408112 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 105525155 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 562197495 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 16710779 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 125893395 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 45735070 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 12243 # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts 3027450313 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 24999 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 125893395 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 441381944 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 37599884 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 466637 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 540742593 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 69650483 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2947282074 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 91 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 4813438 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 54199144 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2931640163 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 14025190740 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 13455020985 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 570169755 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1993140090 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 938500073 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 22029 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 19516 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 179002715 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 971623898 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 487434291 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 36825257 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 41359268 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2792194659 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 28248 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 2432796766 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 13281338 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 894337134 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 2316040320 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 6864 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1215734936 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.001091 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.872110 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 379743334 31.24% 31.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 183587297 15.10% 46.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 204204940 16.80% 63.13% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 169567149 13.95% 77.08% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 132821991 10.93% 88.01% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 92473374 7.61% 95.61% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 37933065 3.12% 98.73% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 12385370 1.02% 99.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 3018416 0.25% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1215734936 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 717080 0.82% 0.82% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 24380 0.03% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.85% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 55165781 62.93% 63.78% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 31749638 36.22% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1103940359 45.38% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 11224025 0.46% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 45.84% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 6876475 0.28% 46.18% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 5502268 0.23% 46.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.40% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 23395329 0.96% 47.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 838660213 34.47% 81.84% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 441822804 18.16% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 2432796766 # Type of FU issued
system.cpu.iq.rate 1.933415 # Inst issue rate
system.cpu.iq.fu_busy_cnt 87656879 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.036031 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 6059775624 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3603986878 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 2248220965 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 122491061 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 82640163 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 56428970 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 2457145320 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 63308325 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 84445856 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 340236717 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 10068 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 1429873 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 210438994 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 345 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 125893395 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 15644195 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1562618 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2792235356 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1396921 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 971623898 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 487434291 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 18262 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1558827 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 2523 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 1429873 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 32450935 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 1518228 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 33969163 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 2357455643 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 792848546 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 75341123 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 12449 # number of nop insts executed
system.cpu.iew.exec_refs 1216025241 # number of memory reference insts executed
system.cpu.iew.exec_branches 319732380 # Number of branches executed
system.cpu.iew.exec_stores 423176695 # Number of stores executed
system.cpu.iew.exec_rate 1.873540 # Inst execution rate
system.cpu.iew.wb_sent 2330413186 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 2304649935 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1347862197 # num instructions producing a value
system.cpu.iew.wb_consumers 2523443205 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.831573 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534136 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitSquashedInsts 906899118 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 21384 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 30614902 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1089841541 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.729918 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.397219 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 449517068 41.25% 41.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 288638854 26.48% 67.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 95107207 8.73% 76.46% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 70204085 6.44% 82.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 46459856 4.26% 87.16% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 22200640 2.04% 89.20% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 15848625 1.45% 90.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 10985187 1.01% 91.66% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 90880019 8.34% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1089841541 # Number of insts commited each cycle
system.cpu.commit.committedInsts 1384381606 # Number of instructions committed
system.cpu.commit.committedOps 1885336358 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908382478 # Number of memory references committed
system.cpu.commit.loads 631387181 # Number of loads committed
system.cpu.commit.membars 9986 # Number of memory barriers committed
system.cpu.commit.branches 298259106 # Number of branches committed
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1653698867 # Number of committed integer instructions.
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
system.cpu.commit.bw_lim_events 90880019 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3791178653 # The number of ROB reads
system.cpu.rob.rob_writes 5710375191 # The number of ROB writes
system.cpu.timesIdled 353026 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 42554766 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1384370590 # Number of Instructions Simulated
system.cpu.committedOps 1885325342 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1384370590 # Number of Instructions Simulated
system.cpu.cpi 0.908925 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.908925 # CPI: Total CPI of All Threads
system.cpu.ipc 1.100200 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.100200 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 11755248902 # number of integer regfile reads
system.cpu.int_regfile_writes 2218571084 # number of integer regfile writes
system.cpu.fp_regfile_reads 68795959 # number of floating regfile reads
system.cpu.fp_regfile_writes 49541079 # number of floating regfile writes
system.cpu.misc_regfile_reads 1363718123 # number of misc regfile reads
system.cpu.misc_regfile_writes 13772902 # number of misc regfile writes
system.cpu.toL2Bus.throughput 169026080 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 1492742 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 1492741 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 96335 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 4299 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 4299 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 72516 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 72516 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 52382 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3178768 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 3231150 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1538688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 104528128 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 106066816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 106066816 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 275072 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 929281000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 42510998 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2307535978 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
system.cpu.icache.replacements 22361 # number of replacements
system.cpu.icache.tagsinuse 1639.588858 # Cycle average of tags in use
system.cpu.icache.total_refs 335620121 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 24041 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13960.322824 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 1639.588858 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.800580 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.800580 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_misses::cpu.data 1953007 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1953007 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 842413 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 842413 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 2795420 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2795420 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 2795420 # number of overall misses
system.cpu.dcache.overall_misses::total 2795420 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 79048557500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 79048557500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 56325650469 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 56325650469 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 203500 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 203500 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 135374207969 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 135374207969 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 135374207969 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 135374207969 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 695943005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 695943005 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10003 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 10003 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 972878683 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 972878683 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 972878683 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 972878683 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002806 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.002806 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003042 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.003042 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000300 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.002873 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.002873 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.002873 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.002873 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40475.306796 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 40475.306796 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66862.275949 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 66862.275949 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67833.333333 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 48427.144389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 48427.144389 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 48427.144389 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 2558 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 879 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 58 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 89 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.103448 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 9.876404 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 96335 # number of writebacks
system.cpu.dcache.writebacks::total 96335 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 488604 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 488604 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 765599 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 765599 # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 1254203 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 1254203 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 1254203 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 1254203 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464403 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 1464403 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76814 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 76814 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 1541217 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 1541217 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1541217 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1541217 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 42813858522 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 42813858522 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4818359000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4818359000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 47632217522 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 47632217522 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 47632217522 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 47632217522 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002104 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002104 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000277 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.001584 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001584 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.001584 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29236.390886 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29236.390886 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62727.614758 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62727.614758 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30905.587936 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 30905.587936 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------