4d8f4db8d1
Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.
475 lines
14 KiB
C++
475 lines
14 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007-2008 The Florida State University
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Stephen Hines
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*/
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#ifndef __ARCH_ARM_MEM_HH__
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#define __ARCH_ARM_MEM_HH__
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#include "arch/arm/insts/pred_inst.hh"
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namespace ArmISA
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{
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class Swap : public PredOp
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{
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protected:
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IntRegIndex dest;
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IntRegIndex op1;
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IntRegIndex base;
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Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base)
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: PredOp(mnem, _machInst, __opClass),
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dest(_dest), op1(_op1), base(_base)
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{}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// The address is a base register plus an immediate.
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class RfeOp : public PredOp
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{
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public:
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enum AddrMode {
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DecrementAfter,
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DecrementBefore,
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IncrementAfter,
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IncrementBefore
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};
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protected:
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IntRegIndex base;
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AddrMode mode;
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bool wb;
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static const unsigned numMicroops = 2;
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StaticInstPtr *uops;
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RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _base, AddrMode _mode, bool _wb)
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: PredOp(mnem, _machInst, __opClass),
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base(_base), mode(_mode), wb(_wb), uops(NULL)
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{}
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virtual
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~RfeOp()
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{
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delete uops;
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}
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StaticInstPtr
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fetchMicroop(MicroPC microPC)
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{
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assert(uops != NULL && microPC < numMicroops);
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return uops[microPC];
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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// The address is a base register plus an immediate.
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class SrsOp : public PredOp
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{
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public:
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enum AddrMode {
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DecrementAfter,
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DecrementBefore,
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IncrementAfter,
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IncrementBefore
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};
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protected:
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uint32_t regMode;
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AddrMode mode;
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bool wb;
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static const unsigned numMicroops = 2;
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StaticInstPtr *uops;
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SrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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uint32_t _regMode, AddrMode _mode, bool _wb)
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: PredOp(mnem, _machInst, __opClass),
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regMode(_regMode), mode(_mode), wb(_wb), uops(NULL)
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{}
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virtual
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~SrsOp()
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{
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delete uops;
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}
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StaticInstPtr
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fetchMicroop(MicroPC microPC)
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{
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assert(uops != NULL && microPC < numMicroops);
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return uops[microPC];
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}
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std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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class Memory : public PredOp
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{
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public:
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enum AddrMode {
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AddrMd_Offset,
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AddrMd_PreIndex,
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AddrMd_PostIndex
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};
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protected:
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IntRegIndex dest;
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IntRegIndex base;
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bool add;
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static const unsigned numMicroops = 3;
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StaticInstPtr *uops;
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Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _base, bool _add)
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: PredOp(mnem, _machInst, __opClass),
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dest(_dest), base(_base), add(_add), uops(NULL)
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{}
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virtual
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~Memory()
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{
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delete [] uops;
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}
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StaticInstPtr
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fetchMicroop(MicroPC microPC)
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{
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assert(uops != NULL && microPC < numMicroops);
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return uops[microPC];
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}
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virtual void
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printOffset(std::ostream &os) const
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{}
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virtual void
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printDest(std::ostream &os) const
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{
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printReg(os, dest);
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}
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void printInst(std::ostream &os, AddrMode addrMode) const;
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};
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// The address is a base register plus an immediate.
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class MemoryImm : public Memory
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{
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protected:
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int32_t imm;
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MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
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: Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
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{}
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void
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printOffset(std::ostream &os) const
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{
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int32_t pImm = imm;
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if (!add)
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pImm = -pImm;
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ccprintf(os, "#%d", pImm);
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}
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};
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class MemoryExImm : public MemoryImm
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{
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protected:
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IntRegIndex result;
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MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
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result(_result)
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{}
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void
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printDest(std::ostream &os) const
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{
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printReg(os, result);
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os << ", ";
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MemoryImm::printDest(os);
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}
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};
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// The address is a base register plus an immediate.
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class MemoryDImm : public MemoryImm
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{
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protected:
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IntRegIndex dest2;
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MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
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dest2(_dest2)
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{}
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void
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printDest(std::ostream &os) const
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{
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MemoryImm::printDest(os);
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os << ", ";
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printReg(os, dest2);
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}
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};
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class MemoryExDImm : public MemoryDImm
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{
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protected:
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IntRegIndex result;
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MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2,
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_base, _add, _imm), result(_result)
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{}
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void
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printDest(std::ostream &os) const
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{
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printReg(os, result);
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os << ", ";
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MemoryDImm::printDest(os);
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}
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};
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// The address is a shifted register plus an immediate
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class MemoryReg : public Memory
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{
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protected:
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int32_t shiftAmt;
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ArmShiftType shiftType;
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IntRegIndex index;
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MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _base, bool _add,
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int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Memory(mnem, _machInst, __opClass, _dest, _base, _add),
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shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
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{}
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void printOffset(std::ostream &os) const;
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};
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class MemoryDReg : public MemoryReg
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{
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protected:
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IntRegIndex dest2;
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MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add,
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int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index),
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dest2(_dest2)
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{}
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void
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printDest(std::ostream &os) const
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{
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MemoryReg::printDest(os);
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os << ", ";
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printReg(os, dest2);
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}
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};
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template<class Base>
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class MemoryOffset : public Base
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{
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protected:
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MemoryOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
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{}
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MemoryOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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MemoryOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
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{}
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MemoryOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _result,
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IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _result,
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_dest, _dest2, _base, _add, _imm)
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{}
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MemoryOffset(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add,
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int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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this->printInst(ss, Memory::AddrMd_Offset);
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return ss.str();
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}
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};
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template<class Base>
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class MemoryPreIndex : public Base
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{
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protected:
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MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
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{}
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MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
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{}
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MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _result,
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IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _result,
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_dest, _dest2, _base, _add, _imm)
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{}
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MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add,
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int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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this->printInst(ss, Memory::AddrMd_PreIndex);
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return ss.str();
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}
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};
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template<class Base>
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class MemoryPostIndex : public Base
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{
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protected:
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MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
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{}
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MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
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bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
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{}
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MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _result,
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IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add, int32_t _imm)
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: Base(mnem, _machInst, __opClass, _result,
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_dest, _dest2, _base, _add, _imm)
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{}
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MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
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IntRegIndex _base, bool _add,
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int32_t _shiftAmt, ArmShiftType _shiftType,
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IntRegIndex _index)
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: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
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_shiftAmt, _shiftType, _index)
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{}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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std::stringstream ss;
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this->printInst(ss, Memory::AddrMd_PostIndex);
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return ss.str();
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}
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};
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}
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#endif //__ARCH_ARM_INSTS_MEM_HH__
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