Gene WU 4d8f4db8d1 ARM: Use fewer micro-ops for register update loads if possible. ... Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict.		2010-08-25 19:10:42 -05:00
..
branch.hh	ARM: Eliminate the old style branch instructions.	2010-06-02 12:58:03 -05:00
macromem.cc	ARM: Use fewer micro-ops for register update loads if possible.	2010-08-25 19:10:42 -05:00
macromem.hh	ARM: Use fewer micro-ops for register update loads if possible.	2010-08-25 19:10:42 -05:00
mem.cc	ARM: Make some of the trace code more compact	2010-06-02 12:58:18 -05:00
mem.hh	ARM: Use fewer micro-ops for register update loads if possible.	2010-08-25 19:10:42 -05:00
misc.cc	ARM: Get rid of the binary dumping function in utility.hh.	2010-06-02 12:58:17 -05:00
misc.hh	ARM: Make undefined instructions obey predication.	2010-06-02 12:58:16 -05:00
mult.hh	ARM: Add base classes for multiply instructions.	2010-06-02 12:58:03 -05:00
pred_inst.cc	ARM: Get rid of obsoleted predicated inst formats, etc.	2010-06-02 12:58:02 -05:00
pred_inst.hh	ARM: Implement all ARM SIMD instructions.	2010-08-25 19:10:42 -05:00
static_inst.cc	ARM: Don't rely on undefined behavior to get arithmetic right shift.	2010-06-02 12:58:04 -05:00
static_inst.hh	ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.	2010-08-25 19:10:42 -05:00
vfp.cc	ARM: Implement all ARM SIMD instructions.	2010-08-25 19:10:42 -05:00
vfp.hh	ARM: Implement all ARM SIMD instructions.	2010-08-25 19:10:42 -05:00