3ed62ad025
arch/SConscript: Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh. arch/alpha/isa_traits.hh: Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore. base/loader/ecoff_object.cc: base/loader/elf_object.cc: cpu/pc_event.hh: cpu/static_inst.hh: mem/port.hh: sim/faults.cc: sim/system.hh: base/misc.hh isn't included through isa_traits.hh anymore. cpu/simple/cpu.cc: Added include for arch/utility.hh --HG-- extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
157 lines
5.5 KiB
Python
157 lines
5.5 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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import os.path
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# Import build environment variable from SConstruct.
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Import('env')
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# Right now there are no source files immediately in this directory
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sources = []
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#################################################################
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#
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# ISA "switch header" generation.
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#
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# Auto-generate arch headers that include the right ISA-specific
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# header based on the setting of THE_ISA preprocessor variable.
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#
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#################################################################
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# List of headers to generate
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isa_switch_hdrs = Split('''
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arguments.hh
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constants.hh
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faults.hh
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isa_traits.hh
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process.hh
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registerfile.hh
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stacktrace.hh
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tlb.hh
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types.hh
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utility.hh
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vtophys.hh
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''')
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# Generate the header. target[0] is the full path of the output
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# header to generate. 'source' is a dummy variable, since we get the
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# list of ISAs from env['ALL_ISA_LIST'].
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def gen_switch_hdr(target, source, env):
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fname = str(target[0])
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basename = os.path.basename(fname)
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f = open(fname, 'w')
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f.write('#include "arch/isa_specific.hh"\n')
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cond = '#if'
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for isa in env['ALL_ISA_LIST']:
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f.write('%s THE_ISA == %s_ISA\n#include "arch/%s/%s"\n'
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% (cond, isa.upper(), isa, basename))
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cond = '#elif'
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f.write('#else\n#error "THE_ISA not set"\n#endif\n')
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f.close()
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return 0
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# String to print when generating header
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def gen_switch_hdr_string(target, source, env):
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return "Generating ISA switch header " + str(target[0])
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# Build SCons Action object. 'varlist' specifies env vars that this
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# action depends on; when env['ALL_ISA_LIST'] changes these actions
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# should get re-executed.
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switch_hdr_action = Action(gen_switch_hdr, gen_switch_hdr_string,
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varlist=['ALL_ISA_LIST'])
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# Instantiate actions for each header
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for hdr in isa_switch_hdrs:
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env.Command(hdr, [], switch_hdr_action)
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#################################################################
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#
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# Include architecture-specific files.
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#
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#################################################################
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#
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# Build a SCons scanner for ISA files
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#
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import SCons.Scanner
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def ISAScan():
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return SCons.Scanner.Classic("ISAScan",
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"$ISASUFFIXES",
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"SRCDIR",
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'^[ \t]*##[ \t]*include[ \t]*"([^>"]+)"')
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def ISAPath(env, dir, target=None, source=None, a=None):
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return (Dir(env['SRCDIR']), Dir('.'))
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iscan = Scanner(function = ISAScan().scan, skeys = [".isa", ".ISA"],
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path_function = ISAPath)
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env.Append(SCANNERS = iscan)
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#
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# Now create a Builder object that uses isa_parser.py to generate C++
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# output from the ISA description (*.isa) files.
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#
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# Convert to File node to fix path
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isa_parser = File('isa_parser.py')
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cpu_models_file = File('#m5/cpu/cpu_models.py')
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# This sucks in the defintions of the CpuModel objects.
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execfile(cpu_models_file.srcnode().abspath)
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# Several files are generated from the ISA description.
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# We always get the basic decoder and header file.
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isa_desc_gen_files = Split('decoder.cc decoder.hh')
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# We also get an execute file for each selected CPU model.
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isa_desc_gen_files += [CpuModel.dict[cpu].filename
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for cpu in env['CPU_MODELS']]
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# The emitter patches up the sources & targets to include the
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# autogenerated files as targets and isa parser itself as a source.
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def isa_desc_emitter(target, source, env):
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return (isa_desc_gen_files, [isa_parser, cpu_models_file] + source)
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# Pieces are in place, so create the builder.
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isa_desc_builder = Builder(action='$SOURCES $TARGET.dir $CPU_MODELS',
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source_scanner = iscan,
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emitter = isa_desc_emitter)
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env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
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#
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# Now include other ISA-specific sources from the ISA subdirectories.
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#
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isa = env['TARGET_ISA'] # someday this may be a list of ISAs
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# Let the target architecture define what additional sources it needs
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sources += SConscript(os.path.join(isa, 'SConscript'),
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exports = 'env', duplicate = False)
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Return('sources')
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