gem5/src/arch/x86/pagetable_walker.hh
Nilay Vaish 4b32c9fb4d x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
2012-03-01 11:37:03 -06:00

205 lines
7.1 KiB
C++

/*
* Copyright (c) 2007 The Hewlett-Packard Development Company
* All rights reserved.
*
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* licensed hereunder. You may use the software subject to the license
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* modified or unmodified, in source code or in binary form.
*
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* met: redistributions of source code must retain the above copyright
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* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* Authors: Gabe Black
*/
#ifndef __ARCH_X86_PAGE_TABLE_WALKER_HH__
#define __ARCH_X86_PAGE_TABLE_WALKER_HH__
#include <vector>
#include "arch/x86/pagetable.hh"
#include "arch/x86/tlb.hh"
#include "base/fast_alloc.hh"
#include "base/types.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "params/X86PagetableWalker.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
class ThreadContext;
namespace X86ISA
{
class Walker : public MemObject
{
protected:
// Port for accessing memory
class WalkerPort : public Port
{
public:
WalkerPort(const std::string &_name, Walker * _walker) :
Port(_name, _walker), walker(_walker)
{}
protected:
Walker *walker;
bool recvTiming(PacketPtr pkt);
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
void recvRangeChange();
void recvRetry();
bool isSnooping() { return true; }
};
friend class WalkerPort;
WalkerPort port;
// State to track each walk of the page table
class WalkerState : public FastAlloc
{
private:
enum State {
Ready,
Waiting,
// Long mode
LongPML4, LongPDP, LongPD, LongPTE,
// PAE legacy mode
PAEPDP, PAEPD, PAEPTE,
// Non PAE legacy mode with and without PSE
PSEPD, PD, PTE
};
protected:
Walker *walker;
ThreadContext *tc;
RequestPtr req;
State state;
State nextState;
int dataSize;
bool enableNX;
unsigned inflight;
TlbEntry entry;
PacketPtr read;
std::vector<PacketPtr> writes;
Fault timingFault;
TLB::Translation * translation;
BaseTLB::Mode mode;
bool functional;
bool timing;
bool retrying;
bool started;
public:
WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
RequestPtr _req, bool _isFunctional = false) :
walker(_walker), req(_req), state(Ready),
nextState(Ready), inflight(0),
translation(_translation),
functional(_isFunctional), timing(false),
retrying(false), started(false)
{
}
void initState(ThreadContext * _tc, BaseTLB::Mode _mode,
bool _isTiming = false);
Fault startWalk();
Fault startFunctional(Addr &addr, Addr &pageSize);
bool recvPacket(PacketPtr pkt);
bool isRetrying();
bool wasStarted();
bool isTiming();
void retry();
std::string name() const {return walker->name();}
private:
void setupWalk(Addr vaddr);
Fault stepWalk(PacketPtr &write);
void sendPackets();
void endWalk();
Fault pageFault(bool present);
};
friend class WalkerState;
// State for timing and atomic accesses (need multiple per walker in
// the case of multiple outstanding requests in timing mode)
std::list<WalkerState *> currStates;
// State for functional accesses (only need one of these per walker)
WalkerState funcState;
struct WalkerSenderState : public Packet::SenderState
{
WalkerState * senderWalk;
Packet::SenderState * saved;
WalkerSenderState(WalkerState * _senderWalk,
Packet::SenderState * _saved) :
senderWalk(_senderWalk), saved(_saved) {}
};
public:
// Kick off the state machine.
Fault start(ThreadContext * _tc, BaseTLB::Translation *translation,
RequestPtr req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
Addr &pageSize, BaseTLB::Mode mode);
Port *getPort(const std::string &if_name, int idx = -1);
protected:
// The TLB we're supposed to load.
TLB * tlb;
System * sys;
MasterID masterId;
// Functions for dealing with packets.
bool recvTiming(PacketPtr pkt);
void recvRetry();
bool sendTiming(WalkerState * sendingState, PacketPtr pkt);
public:
void setTLB(TLB * _tlb)
{
tlb = _tlb;
}
typedef X86PagetableWalkerParams Params;
const Params *
params() const
{
return static_cast<const Params *>(_params);
}
Walker(const Params *params) :
MemObject(params), port(name() + ".port", this),
funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
masterId(sys->getMasterId(name()))
{
}
};
}
#endif // __ARCH_X86_PAGE_TABLE_WALKER_HH__