626 lines
16 KiB
C++
626 lines
16 KiB
C++
/*
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* Copyright (c) 2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_OOO_CPU_OOO_CPU_HH__
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#define __CPU_OOO_CPU_OOO_CPU_HH__
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "encumbered/cpu/full/fu_pool.hh"
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#include "cpu/ooo_cpu/ea_list.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/static_inst.hh"
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#include "mem/mem_interface.hh"
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#include "sim/eventq.hh"
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// forward declarations
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#if FULL_SYSTEM
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class Processor;
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class AlphaITB;
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class AlphaDTB;
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class PhysicalMemory;
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class RemoteGDB;
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class GDBListener;
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#else
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class Process;
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#endif // FULL_SYSTEM
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class Checkpoint;
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class MemInterface;
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namespace Trace {
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class InstRecord;
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}
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/**
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* Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
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* simple out-of-order capabilities added to it. It is still a 1 CPI machine
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* (?), but is capable of handling cache misses. Basically it models having
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* a ROB/IQ by only allowing a certain amount of instructions to execute while
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* the cache miss is outstanding.
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*/
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template <class Impl>
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class OoOCPU : public BaseCPU
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{
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private:
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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public:
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// main simulation loop (one cycle)
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void tick();
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private:
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struct TickEvent : public Event
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{
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OoOCPU *cpu;
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int width;
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TickEvent(OoOCPU *c, int w);
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int delay)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + delay);
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + delay);
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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private:
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Trace::InstRecord *traceData;
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template<typename T>
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void trace_data(T data);
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public:
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//
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enum Status {
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Running,
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Idle,
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IcacheMiss,
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IcacheMissComplete,
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DcacheMissStall,
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SwitchedOut
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};
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private:
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Status _status;
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public:
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void post_interrupt(int int_num, int index);
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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struct Params : public BaseCPU::Params
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{
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MemInterface *icache_interface;
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MemInterface *dcache_interface;
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int width;
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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FunctionalMemory *mem;
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#else
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Process *process;
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#endif
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int issueWidth;
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};
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OoOCPU(Params *params);
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virtual ~OoOCPU();
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void init();
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private:
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void copyFromXC();
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public:
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// execution context
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ExecContext *xc;
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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#endif
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// L1 instruction cache
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MemInterface *icacheInterface;
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// L1 data cache
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MemInterface *dcacheInterface;
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FuncUnitPool *fuPool;
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// Refcounted pointer to the one memory request.
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MemReqPtr cacheMemReq;
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class ICacheCompletionEvent : public Event
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{
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private:
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OoOCPU *cpu;
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public:
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ICacheCompletionEvent(OoOCPU *_cpu);
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virtual void process();
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virtual const char *description();
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};
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// Will need to create a cache completion event upon any memory miss.
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ICacheCompletionEvent iCacheCompletionEvent;
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class DCacheCompletionEvent;
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typedef typename
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std::list<DCacheCompletionEvent>::iterator DCacheCompEventIt;
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class DCacheCompletionEvent : public Event
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{
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private:
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OoOCPU *cpu;
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DynInstPtr inst;
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DCacheCompEventIt dcceIt;
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public:
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DCacheCompletionEvent(OoOCPU *_cpu, DynInstPtr &_inst,
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DCacheCompEventIt &_dcceIt);
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virtual void process();
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virtual const char *description();
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};
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friend class DCacheCompletionEvent;
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protected:
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std::list<DCacheCompletionEvent> dCacheCompList;
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DCacheCompEventIt dcceIt;
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private:
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Status status() const { return _status; }
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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virtual void deallocateContext(int thread_num);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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Counter numInst;
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Counter startNumInst;
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Stats::Scalar<> numInsts;
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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// number of simulated memory references
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Stats::Scalar<> numMemRefs;
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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// number of cycles stalled for I-cache misses
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Stats::Scalar<> icacheStallCycles;
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Counter lastIcacheStall;
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// number of cycles stalled for D-cache misses
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Stats::Scalar<> dcacheStallCycles;
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Counter lastDcacheStall;
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void processICacheCompletion();
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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bool validInstAddr(Addr addr) { return true; }
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bool validDataAddr(Addr addr) { return true; }
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int getInstAsid() { return xc->regs.instAsid(); }
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int getDataAsid() { return xc->regs.dataAsid(); }
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Fault translateInstReq(MemReqPtr &req)
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{
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return itb->translate(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dtb->translate(req, false);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dtb->translate(req, true);
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}
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#else
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bool validInstAddr(Addr addr)
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{ return xc->validInstAddr(addr); }
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bool validDataAddr(Addr addr)
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{ return xc->validDataAddr(addr); }
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int getInstAsid() { return xc->asid; }
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int getDataAsid() { return xc->asid; }
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#endif
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags,
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uint64_t *res, DynInstPtr inst);
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size, unsigned flags)
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{
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// need to do this...
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}
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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private:
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bool executeInst(DynInstPtr &inst);
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void renameInst(DynInstPtr &inst);
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void addInst(DynInstPtr &inst);
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void commitHeadInst();
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bool getOneInst();
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Fault fetchCacheLine();
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InstSeqNum getAndIncrementInstSeq();
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bool ambigMemAddr;
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private:
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InstSeqNum globalSeqNum;
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DynInstPtr renameTable[TheISA::TotalNumRegs];
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DynInstPtr commitTable[TheISA::TotalNumRegs];
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// Might need a table of the shadow registers as well.
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#if FULL_SYSTEM
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DynInstPtr palShadowTable[TheISA::NumIntRegs];
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#endif
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public:
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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// In the OoO case these shouldn't read from the XC but rather from the
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// rename table of DynInsts. Also these likely shouldn't be called very
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// often, other than when adding things into the xc during say a syscall.
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uint64_t readIntReg(StaticInst *si, int idx)
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{
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return xc->readIntReg(si->srcRegIdx(idx));
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}
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float readFloatRegSingle(StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegSingle(reg_idx);
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}
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double readFloatRegDouble(StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegDouble(reg_idx);
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}
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uint64_t readFloatRegInt(StaticInst *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegInt(reg_idx);
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}
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void setIntReg(StaticInst *si, int idx, uint64_t val)
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{
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xc->setIntReg(si->destRegIdx(idx), val);
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}
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void setFloatRegSingle(StaticInst *si, int idx, float val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegSingle(reg_idx, val);
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}
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void setFloatRegDouble(StaticInst *si, int idx, double val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegDouble(reg_idx, val);
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}
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void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegInt(reg_idx, val);
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}
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uint64_t readPC() { return PC; }
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void setNextPC(Addr val) { nextPC = val; }
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private:
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Addr PC;
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Addr nextPC;
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unsigned issueWidth;
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bool fetchRedirExcp;
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bool fetchRedirBranch;
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/** Mask to get a cache block's address. */
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Addr cacheBlkMask;
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unsigned cacheBlkSize;
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Addr cacheBlkPC;
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/** The cache line being fetched. */
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uint8_t *cacheData;
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protected:
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bool cacheBlkValid;
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private:
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// Align an address (typically a PC) to the start of an I-cache block.
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// We fold in the PISA 64- to 32-bit conversion here as well.
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Addr icacheBlockAlignPC(Addr addr)
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{
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addr = TheISA::realPCToFetchPC(addr);
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return (addr & ~(cacheBlkMask));
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}
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unsigned instSize;
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// ROB tracking stuff.
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DynInstPtr robHeadPtr;
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DynInstPtr robTailPtr;
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unsigned robSize;
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unsigned robInsts;
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// List of outstanding EA instructions.
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protected:
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EAList eaList;
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public:
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void branchToTarget(Addr val)
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{
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if (!fetchRedirExcp) {
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fetchRedirBranch = true;
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PC = val;
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}
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}
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// ISA stuff:
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uint64_t readUniq() { return xc->readUniq(); }
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void setUniq(uint64_t val) { xc->setUniq(val); }
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uint64_t readFpcr() { return xc->readFpcr(); }
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void setFpcr(uint64_t val) { xc->setFpcr(val); }
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#if FULL_SYSTEM
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uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
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Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
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Fault hwrei() { return xc->hwrei(); }
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int readIntrFlag() { return xc->readIntrFlag(); }
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void setIntrFlag(int val) { xc->setIntrFlag(val); }
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bool inPalMode() { return xc->inPalMode(); }
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void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
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bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
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#else
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void syscall() { xc->syscall(); }
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#endif
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ExecContext *xcBase() { return xc; }
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};
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// precise architected memory state accessor macros
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template <class Impl>
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template <class T>
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Fault
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OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
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{
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MemReqPtr readReq = new MemReq();
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readReq->xc = xc;
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readReq->asid = 0;
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readReq->data = new uint8_t[64];
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readReq->reset(addr, sizeof(T), flags);
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// translate to physical address - This might be an ISA impl call
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Fault fault = translateDataReadReq(readReq);
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// do functional access
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if (fault == NoFault)
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fault = xc->mem->read(readReq, data);
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#if 0
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if (traceData) {
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traceData->setAddr(addr);
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if (fault == NoFault)
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traceData->setData(data);
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}
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#endif
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// if we have a cache, do cache access too
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if (fault == NoFault && dcacheInterface) {
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readReq->cmd = Read;
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readReq->completionEvent = NULL;
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readReq->time = curTick;
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/*MemAccessResult result = */dcacheInterface->access(readReq);
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if (dcacheInterface->doEvents()) {
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readReq->completionEvent = new DCacheCompletionEvent(this, inst,
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dcceIt);
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}
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}
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if (!dcacheInterface && (readReq->flags & UNCACHEABLE))
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recordEvent("Uncached Read");
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return fault;
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}
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template <class Impl>
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template <class T>
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Fault
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OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
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uint64_t *res, DynInstPtr inst)
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{
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MemReqPtr writeReq = new MemReq();
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writeReq->xc = xc;
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writeReq->asid = 0;
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writeReq->data = new uint8_t[64];
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#if 0
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|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
traceData->setData(data);
|
|
}
|
|
#endif
|
|
|
|
writeReq->reset(addr, sizeof(T), flags);
|
|
|
|
// translate to physical address
|
|
Fault fault = translateDataWriteReq(writeReq);
|
|
|
|
// do functional access
|
|
if (fault == NoFault)
|
|
fault = xc->write(writeReq, data);
|
|
|
|
if (fault == NoFault && dcacheInterface) {
|
|
writeReq->cmd = Write;
|
|
memcpy(writeReq->data,(uint8_t *)&data,writeReq->size);
|
|
writeReq->completionEvent = NULL;
|
|
writeReq->time = curTick;
|
|
/*MemAccessResult result = */dcacheInterface->access(writeReq);
|
|
|
|
if (dcacheInterface->doEvents()) {
|
|
writeReq->completionEvent = new DCacheCompletionEvent(this, inst,
|
|
dcceIt);
|
|
}
|
|
}
|
|
|
|
if (res && (fault == NoFault))
|
|
*res = writeReq->result;
|
|
|
|
if (!dcacheInterface && (writeReq->flags & UNCACHEABLE))
|
|
recordEvent("Uncached Write");
|
|
|
|
return fault;
|
|
}
|
|
|
|
|
|
#endif // __CPU_OOO_CPU_OOO_CPU_HH__
|