Mitch Hayenga 4a752b1655 arm: add access syscall for ARM SE mode ... This patch adds the "access" syscall for ARM SE as required by some spec2006 benchmarks.		2013-01-08 08:54:07 -05:00
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alpha	arch: Move the ISA object to a separate section	2013-01-07 13:05:42 -05:00
arm	arm: add access syscall for ARM SE mode	2013-01-08 08:54:07 -05:00
generic	arch: Fix broken M5VarArgsFault initialization	2013-01-07 13:05:38 -05:00
mips	arch: Move the ISA object to a separate section	2013-01-07 13:05:42 -05:00
noisa	cpu: add separate stats for insts/ops both globally and per cpu model	2012-02-12 16:07:39 -06:00
power	arch: Move the ISA object to a separate section	2013-01-07 13:05:42 -05:00
sparc	cpu: Flush TLBs on switchOut()	2013-01-07 13:05:48 -05:00
x86	arch: Move the ISA object to a separate section	2013-01-07 13:05:42 -05:00
isa_parser.py	O3: Clean up the O3 structures and try to pack them a bit better.	2012-06-05 01:23:09 -04:00
micro_asm.py	scons: add slicc and ply to sys.path and PYTHONPATH so everyone has access	2009-09-22 15:24:16 -07:00
micro_asm_test.py	Add a second section to make sure the ROM is extended properly.	2007-05-31 22:21:21 +00:00
SConscript	CPU: Merge the predecoder and decoder.	2012-05-26 13:44:46 -07:00