397 lines
45 KiB
Plaintext
397 lines
45 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000021 # Number of seconds simulated
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sim_ticks 21234500 # Number of ticks simulated
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final_tick 21234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 37422 # Simulator instruction rate (inst/s)
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host_op_rate 37415 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 124041463 # Simulator tick rate (ticks/s)
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host_mem_usage 214024 # Number of bytes of host memory used
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host_seconds 0.17 # Real time elapsed on the host
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sim_insts 6404 # Number of instructions simulated
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sim_ops 6404 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 30016 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 469 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 1413548706 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 907202901 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 1413548706 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 1186 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 1193 # DTB read accesses
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system.cpu.dtb.write_hits 898 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 901 # DTB write accesses
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system.cpu.dtb.data_hits 2084 # DTB hits
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system.cpu.dtb.data_misses 10 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 2094 # DTB accesses
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system.cpu.itb.fetch_hits 908 # ITB hits
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system.cpu.itb.fetch_misses 17 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 925 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 42470 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.lookups 1608 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 1127 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 712 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1187 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 26.453243 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 1144 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5213 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 4580 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9793 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 2970 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 2183 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 367 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 651 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 401 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 61.882129 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 4474 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 11434 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 443 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 35079 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 7391 # Number of cycles cpu stages are processed.
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system.cpu.activity 17.402873 # Percentage of cycles cpu is active
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system.cpu.comLoads 1185 # Number of Load instructions committed
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system.cpu.comStores 865 # Number of Store instructions committed
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system.cpu.comBranches 1051 # Number of Branches instructions committed
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system.cpu.comNops 17 # Number of Nop instructions committed
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system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
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system.cpu.comInts 3265 # Number of Integer instructions committed
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system.cpu.comFloats 2 # Number of Floating Point instructions committed
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system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total)
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system.cpu.cpi 6.631793 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi nan # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.631793 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.150789 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc nan # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.150789 # IPC: Total IPC of All Threads
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system.cpu.stage0.idleCycles 37550 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4920 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 11.584648 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 38585 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3885 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 9.147634 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 38290 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 4180 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 9.842242 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 41130 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 3.155168 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 38002 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 4468 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 10.520367 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 138.955928 # Cycle average of tags in use
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system.cpu.icache.total_refs 558 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 138.955928 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.067850 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.067850 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits
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system.cpu.icache.overall_hits::total 558 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses
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system.cpu.icache.overall_misses::total 350 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 19343500 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 19343500 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 19343500 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 19343500 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 19343500 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 19343500 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55267.142857 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55267.142857 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16051500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 16051500 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16051500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 16051500 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16051500 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 16051500 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53150.662252 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53150.662252 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 102.711534 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1703 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 102.711534 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.025076 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.025076 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 615 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 615 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 1703 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 1703 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 1703 # number of overall hits
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system.cpu.dcache.overall_hits::total 1703 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 250 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 250 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 347 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 347 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 347 # number of overall misses
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system.cpu.dcache.overall_misses::total 347 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 5507500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 5507500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 13555000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 13555000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 19062500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 19062500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 19062500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 19062500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 1185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 1185 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 2050 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 2050 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 2050 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 2050 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081857 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289017 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.169268 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.169268 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56778.350515 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54220 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 54935.158501 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 1656000 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 36 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 46000 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::cpu.data 177 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 177 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::cpu.data 179 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 179 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::cpu.data 179 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 179 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5113000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5113000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3909500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 3909500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9022500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9022500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9022500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 9022500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53821.052632 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53554.794521 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53705.357143 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 195.300582 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 139.031748 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 56.268833 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004243 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.005960 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15708000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4994000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3821500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 3821500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15708000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 8815500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 24523500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15708000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 8815500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 24523500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52186.046512 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52568.421053 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52349.315068 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52186.046512 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52473.214286 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15876500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6780500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 18819000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6780500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 18819000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40400 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40360.119048 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|