gem5/configs/common
Ali Saidi 0dfc29a023 fix partial writes with a functional memory hack
figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached

configs/common/FSConfig.py:
src/mem/bridge.cc:
src/mem/bridge.hh:
src/python/m5/objects/Bridge.py:
    fix partial writes with a functional memory hack
src/mem/bus.cc:
src/mem/bus.hh:
src/python/m5/objects/Bus.py:
    figure out the block size from devices attached to the bus otherwise use a default block size when no devices that care are attached
src/mem/packet.cc:
    fix WriteInvalidateResp to not be a request that needs a response since it isn't
src/mem/port.hh:
    by default return 0 for deviceBlockSize instead of panicing. This makes finding the block size the bus should use easier

--HG--
extra : convert_revision : 3fcfe95f9f392ef76f324ee8bd1d7f6de95c1a64
2007-05-07 14:42:03 -04:00
..
Benchmarks.py add a udp stream benchmark and a udp loopback benchmark 2007-04-30 13:08:21 -04:00
Caches.py Add L2 cache option to fs.py --l2cache 2006-11-15 18:22:15 -05:00
cpu2000.py Fix mcf benchmark object so it gets the arguments it expects. 2007-03-22 00:10:47 -04:00
FSConfig.py fix partial writes with a functional memory hack 2007-05-07 14:42:03 -04:00
Options.py decouple the switch option from the warmup period option - parsing was confused otherwise, oops. 2006-10-30 14:12:15 -05:00
Simulation.py Move all of the parameters of the Root SimObject so they are 2007-03-06 11:13:43 -08:00
SysPaths.py make rcS files read from the m5 source directory, not /dist. 2006-11-08 14:10:25 -05:00