This patch is the last part of moving all protocol-related functionality out of the Port base class. All the send/recv functions are already moved, and the retry (which still governs all the timing transport functions) is the only part that remained in the base class. The only point where this currently causes a bit of inconvenience is in the bus where the retry list is global and holds Port pointers (not Master/SlavePort). This is about to change with the split into a request/response bus and will soon be removed anyway. The patch has no impact on any regressions.
224 lines
5.2 KiB
C++
224 lines
5.2 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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* Andreas Hansson
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* William Wang
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*/
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/**
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* @file
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* Port object definitions.
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*/
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#include "base/trace.hh"
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#include "mem/mem_object.hh"
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#include "mem/port.hh"
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Port::Port(const std::string &_name, MemObject& _owner, PortID _id)
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: portName(_name), id(_id), owner(_owner)
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{
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}
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Port::~Port()
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{
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}
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/**
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* Master port
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*/
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MasterPort::MasterPort(const std::string& name, MemObject* owner, PortID _id)
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: Port(name, *owner, _id), _slavePort(NULL)
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{
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}
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MasterPort::~MasterPort()
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{
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}
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SlavePort&
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MasterPort::getSlavePort() const
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{
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if(_slavePort == NULL)
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panic("Cannot getSlavePort on master port %s that is not connected\n",
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name());
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return *_slavePort;
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}
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void
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MasterPort::bind(SlavePort& slave_port)
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{
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// master port keeps track of the slave port
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_slavePort = &slave_port;
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// slave port also keeps track of master port
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_slavePort->bind(*this);
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}
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bool
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MasterPort::isConnected() const
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{
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return _slavePort != NULL;
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}
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unsigned
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MasterPort::peerBlockSize() const
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{
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return _slavePort->deviceBlockSize();
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}
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Tick
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MasterPort::sendAtomic(PacketPtr pkt)
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{
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assert(pkt->isRequest());
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return _slavePort->recvAtomic(pkt);
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}
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void
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MasterPort::sendFunctional(PacketPtr pkt)
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{
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assert(pkt->isRequest());
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return _slavePort->recvFunctional(pkt);
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}
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bool
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MasterPort::sendTimingReq(PacketPtr pkt)
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{
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assert(pkt->isRequest());
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return _slavePort->recvTimingReq(pkt);
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}
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bool
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MasterPort::sendTimingSnoopResp(PacketPtr pkt)
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{
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assert(pkt->isResponse());
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return _slavePort->recvTimingSnoopResp(pkt);
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}
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void
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MasterPort::sendRetry()
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{
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_slavePort->recvRetry();
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}
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void
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MasterPort::printAddr(Addr a)
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{
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Request req(a, 1, 0, Request::funcMasterId);
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Packet pkt(&req, MemCmd::PrintReq);
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Packet::PrintReqState prs(std::cerr);
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pkt.senderState = &prs;
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sendFunctional(&pkt);
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}
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/**
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* Slave port
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*/
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SlavePort::SlavePort(const std::string& name, MemObject* owner, PortID id)
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: Port(name, *owner, id), _masterPort(NULL)
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{
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}
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SlavePort::~SlavePort()
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{
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}
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void
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SlavePort::bind(MasterPort& master_port)
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{
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_masterPort = &master_port;
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}
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MasterPort&
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SlavePort::getMasterPort() const
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{
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if (_masterPort == NULL)
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panic("Cannot getMasterPort on slave port %s that is not connected\n",
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name());
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return *_masterPort;
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}
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unsigned
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SlavePort::peerBlockSize() const
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{
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return _masterPort->deviceBlockSize();
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}
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bool
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SlavePort::isConnected() const
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{
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return _masterPort != NULL;
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}
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Tick
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SlavePort::sendAtomicSnoop(PacketPtr pkt)
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{
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assert(pkt->isRequest());
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return _masterPort->recvAtomicSnoop(pkt);
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}
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void
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SlavePort::sendFunctionalSnoop(PacketPtr pkt)
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{
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assert(pkt->isRequest());
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return _masterPort->recvFunctionalSnoop(pkt);
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}
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bool
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SlavePort::sendTimingResp(PacketPtr pkt)
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{
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assert(pkt->isResponse());
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return _masterPort->recvTimingResp(pkt);
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}
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void
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SlavePort::sendTimingSnoopReq(PacketPtr pkt)
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{
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assert(pkt->isRequest());
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_masterPort->recvTimingSnoopReq(pkt);
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}
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void
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SlavePort::sendRetry()
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{
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_masterPort->recvRetry();
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}
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