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gem5/src/mem
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Andreas Hansson 49407d76aa Port: Add isSnooping to slave port (asking master port) 
This patch adds isSnooping to the slave port, and thus avoids going
through getMasterPort to be able to ask the master. Over the course of
the next few patches, all getMasterPort/getSlavePort in Port and
MemObject are to be protocol agnostic, and the snooping is part of the
protocol layer.

The function is already present on the master port, where it is
implemented by the module itself, e.g. a cache. On the slave side, it
is merely asking the connected master port. The same name is used by
both functions despite their difference in behaviour. The initial
design used isMasterSnooping on the slave port side, but the more
verbose function name was later changed.
2012-07-09 12:35:32 -04:00
..
cache Port: Add isSnooping to slave port (asking master port) 2012-07-09 12:35:32 -04:00
config Fixes to get prefetching working again. 2009-02-16 08:56:40 -08:00
protocol MOESI_hammer: tbe allocation and dependent wakeup fixes 2012-04-06 13:47:07 -07:00
ruby Port: Add isSnooping to slave port (asking master port) 2012-07-09 12:35:32 -04:00
slicc clang/gcc: Fix compilation issues with clang 3.0 and gcc 4.6 2012-04-14 05:43:31 -04:00
abstract_mem.cc Mem: Fix a livelock resulting in LLSC/locked memory access implementation. 2012-06-29 11:19:05 -04:00
abstract_mem.hh Mem: add per-master stats to physmem 2012-06-05 01:23:11 -04:00
AbstractMemory.py MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
bridge.cc Bridge: Split deferred request, response and sender state 2012-05-30 05:28:06 -04:00
bridge.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
Bridge.py MEM: Introduce the master/slave port roles in the Python classes 2012-02-13 06:43:09 -05:00
bus.cc Port: Move retry from port base class to Master/SlavePort 2012-07-09 12:35:31 -04:00
bus.hh Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
Bus.py Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
coherent_bus.cc Port: Add isSnooping to slave port (asking master port) 2012-07-09 12:35:32 -04:00
coherent_bus.hh Bus: enable non/coherent buses sub-classes 2012-06-29 11:19:08 -04:00
comm_monitor.cc Port: Add isSnooping to slave port (asking master port) 2012-07-09 12:35:32 -04:00
comm_monitor.hh MEM: Add the communication monitor 2012-05-09 04:37:45 -04:00
CommMonitor.py MEM: Add the communication monitor 2012-05-09 04:37:45 -04:00
fs_translating_port_proxy.cc mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
MemObject.py Major changes to how SimObjects are created and initialized. Almost all 2007-07-23 21:51:38 -07:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
noncoherent_bus.cc Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
noncoherent_bus.hh Bus: enable non/coherent buses sub-classes 2012-06-29 11:19:08 -04:00
packet.cc Packet: Cleaning up packet command and attribute 2012-05-23 09:18:04 -04:00
packet.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
packet_queue.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
page_table.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
page_table.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
physical.cc MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
physical.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
port.cc Port: Move retry from port base class to Master/SlavePort 2012-07-09 12:35:31 -04:00
port.hh Port: Add isSnooping to slave port (asking master port) 2012-07-09 12:35:32 -04:00
port_proxy.cc MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
request.hh sim: Remove FastAlloc 2012-06-05 01:23:08 -04:00
SConscript Bus: Split the bus into a non-coherent and coherent bus 2012-05-31 13:30:04 -04:00
se_translating_port_proxy.cc MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
simple_mem.cc MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
simple_mem.hh MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
SimpleMemory.py MEM: Enable multiple distributed generalized memories 2012-04-06 13:46:31 -04:00
tport.cc mem: Delay deleting of incoming packets by one call. 2012-06-07 10:59:03 -04:00
tport.hh mem: Delay deleting of incoming packets by one call. 2012-06-07 10:59:03 -04:00