9e3d79694c
Constructor takes a bool to signify that it is either a cpu_request or not a cpu_request.
When accedding variables of a cpu_request it asserts that it is a cpu_request.
It also asserts that a value being read has been written at some point in time prior (not gaurnteeing it is up to date, but it was at least written before read).
There is also a isCpuReq() function to determine if this is a cpu_request. It should be called before accesing a cpu_request only variable.
SConscript:
Add compilation support for request.cc
arch/alpha/tlb.cc:
arch/alpha/tlb.hh:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/io_device.cc:
mem/page_table.cc:
mem/page_table.hh:
mem/port.cc:
Update for unified request object and accessor functions.
mem/request.hh:
Remove CpuRequest, make it a unified object. Make variables private with accessor functions.
May want to move things from .cc file into header (usually a assert() and either returning a value, or writting two).
--HG--
extra : convert_revision : f1e45cc490dadc7a418634539b03c3e72684a6e3
450 lines
14 KiB
C++
450 lines
14 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_EXEC_CONTEXT_HH__
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#define __CPU_EXEC_CONTEXT_HH__
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#include "config/full_system.hh"
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#include "mem/request.hh"
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#include "sim/faults.hh"
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#include "sim/host.hh"
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#include "sim/serialize.hh"
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#include "sim/byteswap.hh"
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// @todo: Figure out a more architecture independent way to obtain the ITB and
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// DTB pointers.
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class AlphaDTB;
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class AlphaITB;
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class BaseCPU;
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class Event;
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class TranslatingPort;
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class FunctionalPort;
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class VirtualPort;
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class Process;
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class System;
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class ExecContext
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{
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protected:
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscRegFile MiscRegFile;
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typedef TheISA::MiscReg MiscReg;
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public:
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enum Status
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{
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/// Initialized but not running yet. All CPUs start in
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/// this state, but most transition to Active on cycle 1.
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/// In MP or SMT systems, non-primary contexts will stay
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/// in this state until a thread is assigned to them.
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Unallocated,
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/// Running. Instructions should be executed only when
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/// the context is in this state.
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Active,
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/// Temporarily inactive. Entered while waiting for
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/// synchronization, etc.
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Suspended,
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/// Permanently shut down. Entered when target executes
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/// m5exit pseudo-instruction. When all contexts enter
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/// this state, the simulation will terminate.
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Halted
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};
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virtual ~ExecContext() { };
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virtual BaseCPU *getCpuPtr() = 0;
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virtual void setCpuId(int id) = 0;
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virtual int readCpuId() = 0;
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#if FULL_SYSTEM
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virtual System *getSystemPtr() = 0;
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virtual AlphaITB *getITBPtr() = 0;
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virtual AlphaDTB * getDTBPtr() = 0;
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virtual FunctionalPort *getPhysPort() = 0;
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virtual VirtualPort *getVirtPort(ExecContext *xc = NULL) = 0;
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virtual void delVirtPort(VirtualPort *vp) = 0;
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#else
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virtual TranslatingPort *getMemPort() = 0;
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virtual Process *getProcessPtr() = 0;
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#endif
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virtual Status status() const = 0;
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virtual void setStatus(Status new_status) = 0;
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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virtual void activate(int delay = 1) = 0;
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/// Set the status to Suspended.
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virtual void suspend() = 0;
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/// Set the status to Unallocated.
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virtual void deallocate() = 0;
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/// Set the status to Halted.
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virtual void halt() = 0;
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#if FULL_SYSTEM
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virtual void dumpFuncProfile() = 0;
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#endif
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virtual void takeOverFrom(ExecContext *old_context) = 0;
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virtual void regStats(const std::string &name) = 0;
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virtual void serialize(std::ostream &os) = 0;
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virtual void unserialize(Checkpoint *cp, const std::string §ion) = 0;
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#if FULL_SYSTEM
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virtual Event *getQuiesceEvent() = 0;
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// Not necessarily the best location for these...
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// Having an extra function just to read these is obnoxious
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virtual Tick readLastActivate() = 0;
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virtual Tick readLastSuspend() = 0;
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virtual void profileClear() = 0;
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virtual void profileSample() = 0;
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#endif
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virtual int getThreadNum() = 0;
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virtual int getInstAsid() = 0;
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virtual int getDataAsid() = 0;
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virtual Fault translateInstReq(RequestPtr &req) = 0;
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virtual Fault translateDataReadReq(RequestPtr &req) = 0;
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virtual Fault translateDataWriteReq(RequestPtr &req) = 0;
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// Also somewhat obnoxious. Really only used for the TLB fault.
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// However, may be quite useful in SPARC.
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virtual TheISA::MachInst getInst() = 0;
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virtual void copyArchRegs(ExecContext *xc) = 0;
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virtual void clearArchRegs() = 0;
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//
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// New accessors for new decoder.
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//
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virtual uint64_t readIntReg(int reg_idx) = 0;
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virtual FloatReg readFloatReg(int reg_idx, int width) = 0;
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virtual FloatReg readFloatReg(int reg_idx) = 0;
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virtual FloatRegBits readFloatRegBits(int reg_idx, int width) = 0;
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virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
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virtual void setIntReg(int reg_idx, uint64_t val) = 0;
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virtual void setFloatReg(int reg_idx, FloatReg val, int width) = 0;
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virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
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virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width) = 0;
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virtual uint64_t readPC() = 0;
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virtual void setPC(uint64_t val) = 0;
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virtual uint64_t readNextPC() = 0;
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virtual void setNextPC(uint64_t val) = 0;
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virtual uint64_t readNextNPC() = 0;
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virtual void setNextNPC(uint64_t val) = 0;
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virtual MiscReg readMiscReg(int misc_reg) = 0;
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virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
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virtual Fault setMiscReg(int misc_reg, const MiscReg &val) = 0;
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virtual Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val) = 0;
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// Also not necessarily the best location for these two. Hopefully will go
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// away once we decide upon where st cond failures goes.
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virtual unsigned readStCondFailures() = 0;
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virtual void setStCondFailures(unsigned sc_failures) = 0;
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#if FULL_SYSTEM
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virtual int readIntrFlag() = 0;
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virtual void setIntrFlag(int val) = 0;
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virtual Fault hwrei() = 0;
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virtual bool inPalMode() = 0;
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virtual bool simPalCheck(int palFunc) = 0;
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#endif
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// Only really makes sense for old CPU model. Still could be useful though.
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virtual bool misspeculating() = 0;
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#if !FULL_SYSTEM
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virtual IntReg getSyscallArg(int i) = 0;
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// used to shift args for indirect syscall
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virtual void setSyscallArg(int i, IntReg val) = 0;
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virtual void setSyscallReturn(SyscallReturn return_value) = 0;
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virtual void syscall() = 0;
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// Same with st cond failures.
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virtual Counter readFuncExeInst() = 0;
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virtual void setFuncExeInst(Counter new_val) = 0;
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#endif
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virtual void changeRegFileContext(RegFile::ContextParam param,
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RegFile::ContextVal val) = 0;
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};
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template <class XC>
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class ProxyExecContext : public ExecContext
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{
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public:
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ProxyExecContext(XC *actual_xc)
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{ actualXC = actual_xc; }
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private:
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XC *actualXC;
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public:
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BaseCPU *getCpuPtr() { return actualXC->getCpuPtr(); }
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void setCpuId(int id) { actualXC->setCpuId(id); }
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int readCpuId() { return actualXC->readCpuId(); }
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#if FULL_SYSTEM
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System *getSystemPtr() { return actualXC->getSystemPtr(); }
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AlphaITB *getITBPtr() { return actualXC->getITBPtr(); }
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AlphaDTB *getDTBPtr() { return actualXC->getDTBPtr(); }
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FunctionalPort *getPhysPort() { return actualXC->getPhysPort(); }
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VirtualPort *getVirtPort(ExecContext *xc = NULL) { return actualXC->getVirtPort(xc); }
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void delVirtPort(VirtualPort *vp) { return actualXC->delVirtPort(vp); }
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#else
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TranslatingPort *getMemPort() { return actualXC->getMemPort(); }
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Process *getProcessPtr() { return actualXC->getProcessPtr(); }
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#endif
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Status status() const { return actualXC->status(); }
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void setStatus(Status new_status) { actualXC->setStatus(new_status); }
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1) { actualXC->activate(delay); }
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/// Set the status to Suspended.
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void suspend() { actualXC->suspend(); }
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/// Set the status to Unallocated.
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void deallocate() { actualXC->deallocate(); }
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/// Set the status to Halted.
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void halt() { actualXC->halt(); }
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#if FULL_SYSTEM
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void dumpFuncProfile() { actualXC->dumpFuncProfile(); }
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#endif
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void takeOverFrom(ExecContext *oldContext)
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{ actualXC->takeOverFrom(oldContext); }
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void regStats(const std::string &name) { actualXC->regStats(name); }
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void serialize(std::ostream &os) { actualXC->serialize(os); }
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void unserialize(Checkpoint *cp, const std::string §ion)
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{ actualXC->unserialize(cp, section); }
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#if FULL_SYSTEM
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Event *getQuiesceEvent() { return actualXC->getQuiesceEvent(); }
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Tick readLastActivate() { return actualXC->readLastActivate(); }
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Tick readLastSuspend() { return actualXC->readLastSuspend(); }
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void profileClear() { return actualXC->profileClear(); }
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void profileSample() { return actualXC->profileSample(); }
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#endif
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int getThreadNum() { return actualXC->getThreadNum(); }
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int getInstAsid() { return actualXC->getInstAsid(); }
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int getDataAsid() { return actualXC->getDataAsid(); }
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Fault translateInstReq(RequestPtr &req)
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{ return actualXC->translateInstReq(req); }
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Fault translateDataReadReq(RequestPtr &req)
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{ return actualXC->translateDataReadReq(req); }
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Fault translateDataWriteReq(RequestPtr &req)
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{ return actualXC->translateDataWriteReq(req); }
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// @todo: Do I need this?
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MachInst getInst() { return actualXC->getInst(); }
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// @todo: Do I need this?
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void copyArchRegs(ExecContext *xc) { actualXC->copyArchRegs(xc); }
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void clearArchRegs() { actualXC->clearArchRegs(); }
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//
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// New accessors for new decoder.
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//
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uint64_t readIntReg(int reg_idx)
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{ return actualXC->readIntReg(reg_idx); }
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FloatReg readFloatReg(int reg_idx, int width)
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{ return actualXC->readFloatReg(reg_idx, width); }
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FloatReg readFloatReg(int reg_idx)
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{ return actualXC->readFloatReg(reg_idx); }
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FloatRegBits readFloatRegBits(int reg_idx, int width)
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{ return actualXC->readFloatRegBits(reg_idx, width); }
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FloatRegBits readFloatRegBits(int reg_idx)
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{ return actualXC->readFloatRegBits(reg_idx); }
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void setIntReg(int reg_idx, uint64_t val)
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{ actualXC->setIntReg(reg_idx, val); }
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void setFloatReg(int reg_idx, FloatReg val, int width)
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{ actualXC->setFloatReg(reg_idx, val, width); }
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void setFloatReg(int reg_idx, FloatReg val)
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{ actualXC->setFloatReg(reg_idx, val); }
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void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
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{ actualXC->setFloatRegBits(reg_idx, val, width); }
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void setFloatRegBits(int reg_idx, FloatRegBits val)
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{ actualXC->setFloatRegBits(reg_idx, val); }
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uint64_t readPC() { return actualXC->readPC(); }
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void setPC(uint64_t val) { actualXC->setPC(val); }
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uint64_t readNextPC() { return actualXC->readNextPC(); }
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void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
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uint64_t readNextNPC() { return actualXC->readNextNPC(); }
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void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
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MiscReg readMiscReg(int misc_reg)
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{ return actualXC->readMiscReg(misc_reg); }
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
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{ return actualXC->readMiscRegWithEffect(misc_reg, fault); }
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{ return actualXC->setMiscReg(misc_reg, val); }
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{ return actualXC->setMiscRegWithEffect(misc_reg, val); }
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unsigned readStCondFailures()
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{ return actualXC->readStCondFailures(); }
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void setStCondFailures(unsigned sc_failures)
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{ actualXC->setStCondFailures(sc_failures); }
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#if FULL_SYSTEM
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int readIntrFlag() { return actualXC->readIntrFlag(); }
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void setIntrFlag(int val) { actualXC->setIntrFlag(val); }
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Fault hwrei() { return actualXC->hwrei(); }
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bool inPalMode() { return actualXC->inPalMode(); }
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bool simPalCheck(int palFunc) { return actualXC->simPalCheck(palFunc); }
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#endif
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// @todo: Fix this!
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bool misspeculating() { return actualXC->misspeculating(); }
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#if !FULL_SYSTEM
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IntReg getSyscallArg(int i) { return actualXC->getSyscallArg(i); }
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// used to shift args for indirect syscall
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void setSyscallArg(int i, IntReg val)
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{ actualXC->setSyscallArg(i, val); }
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void setSyscallReturn(SyscallReturn return_value)
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{ actualXC->setSyscallReturn(return_value); }
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void syscall() { actualXC->syscall(); }
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Counter readFuncExeInst() { return actualXC->readFuncExeInst(); }
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void setFuncExeInst(Counter new_val)
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{ return actualXC->setFuncExeInst(new_val); }
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#endif
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void changeRegFileContext(RegFile::ContextParam param,
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RegFile::ContextVal val)
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{
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actualXC->changeRegFileContext(param, val);
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}
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};
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#endif
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