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gem5/src/arch/arm/isa/formats
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Gabe Black 48525f581c ARM: Split the condition codes out of the CPSR. 
This allows those bits to be renamed while allowing the other fields to
control the behavior of the processor.
2009-11-08 02:08:40 -08:00
..
basic.isa ARM: Don't downconvert ExtMachInsts to MachInsts. 2009-06-21 16:41:07 -07:00
branch.isa ARM: Split the condition codes out of the CPSR. 2009-11-08 02:08:40 -08:00
formats.isa arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
fp.isa ARM: Split the condition codes out of the CPSR. 2009-11-08 02:08:40 -08:00
macromem.isa ARM: Set up an intregs.hh for ARM. 2009-11-08 00:07:35 -08:00
mem.isa ARM: Improve memory instruction disassembly. 2009-07-08 23:02:19 -07:00
pred.isa ARM: Split the condition codes out of the CPSR. 2009-11-08 02:08:40 -08:00
unimp.isa arm: add ARM support to M5 2009-04-05 18:53:15 -07:00
unknown.isa ARM: Don't downconvert ExtMachInsts to MachInsts. 2009-06-21 16:41:07 -07:00
util.isa ARM: Split the condition codes out of the CPSR. 2009-11-08 02:08:40 -08:00