368 lines
42 KiB
Plaintext
368 lines
42 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000018 # Number of seconds simulated
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sim_ticks 18196500 # Number of ticks simulated
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final_tick 18196500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 90140 # Simulator instruction rate (inst/s)
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host_op_rate 90112 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 306976844 # Simulator tick rate (ticks/s)
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host_mem_usage 211148 # Number of bytes of host memory used
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host_seconds 0.06 # Real time elapsed on the host
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sim_insts 5340 # Number of instructions simulated
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sim_ops 5340 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 27072 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 0 # Number of bytes written to this memory
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system.physmem.num_reads 423 # Number of read requests responded to by this memory
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system.physmem.num_writes 0 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 1487758635 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 1016459209 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total 1487758635 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.workload.num_syscalls 11 # Number of system calls
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system.cpu.numCycles 36394 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 9708 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
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system.cpu.timesIdled 421 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu.idleCycles 30167 # Number of cycles cpu's stages were not processed
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system.cpu.runCycles 6227 # Number of cycles cpu stages are processed.
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system.cpu.activity 17.109963 # Percentage of cycles cpu is active
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system.cpu.comLoads 716 # Number of Load instructions committed
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system.cpu.comStores 673 # Number of Store instructions committed
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system.cpu.comBranches 1116 # Number of Branches instructions committed
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system.cpu.comNops 173 # Number of Nop instructions committed
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system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
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system.cpu.comInts 2537 # Number of Integer instructions committed
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system.cpu.comFloats 0 # Number of Floating Point instructions committed
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system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread)
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system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread)
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system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
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system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total)
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system.cpu.cpi 6.815356 # CPI: Cycles Per Instruction (Per-Thread)
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system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
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system.cpu.cpi_total 6.815356 # CPI: Total CPI of All Threads
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system.cpu.ipc 0.146727 # IPC: Instructions Per Cycle (Per-Thread)
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system.cpu.smt_ipc no_value # IPC: Total SMT-IPC
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system.cpu.ipc_total 0.146727 # IPC: Total IPC of All Threads
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system.cpu.branch_predictor.lookups 1617 # Number of BP lookups
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system.cpu.branch_predictor.condPredicted 1022 # Number of conditional branches predicted
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system.cpu.branch_predictor.condIncorrect 899 # Number of conditional branches incorrect
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system.cpu.branch_predictor.BTBLookups 1172 # Number of BTB lookups
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system.cpu.branch_predictor.BTBHits 435 # Number of BTB hits
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system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target.
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system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions.
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system.cpu.branch_predictor.BTBHitPct 37.116041 # BTB Hit Percentage
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system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 1115 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5634 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 4000 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9634 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 1686 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 1487 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 319 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 517 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 836 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 280 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 74.910394 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 3979 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.stage0.idleCycles 31821 # Number of cycles 0 instructions are processed.
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system.cpu.stage0.runCycles 4573 # Number of cycles 1+ instructions are processed.
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system.cpu.stage0.utilization 12.565258 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage1.idleCycles 33191 # Number of cycles 0 instructions are processed.
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system.cpu.stage1.runCycles 3203 # Number of cycles 1+ instructions are processed.
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system.cpu.stage1.utilization 8.800901 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage2.idleCycles 33344 # Number of cycles 0 instructions are processed.
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system.cpu.stage2.runCycles 3050 # Number of cycles 1+ instructions are processed.
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system.cpu.stage2.utilization 8.380502 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage3.idleCycles 35411 # Number of cycles 0 instructions are processed.
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system.cpu.stage3.runCycles 983 # Number of cycles 1+ instructions are processed.
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system.cpu.stage3.utilization 2.700995 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.stage4.idleCycles 33220 # Number of cycles 0 instructions are processed.
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system.cpu.stage4.runCycles 3174 # Number of cycles 1+ instructions are processed.
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system.cpu.stage4.utilization 8.721218 # Percentage of cycles stage was utilized (processing insts).
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system.cpu.icache.replacements 0 # number of replacements
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system.cpu.icache.tagsinuse 136.672418 # Cycle average of tags in use
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system.cpu.icache.total_refs 827 # Total number of references to valid blocks.
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system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
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system.cpu.icache.avg_refs 2.841924 # Average number of references to valid blocks.
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.icache.occ_blocks::cpu.inst 136.672418 # Average occupied blocks per requestor
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system.cpu.icache.occ_percent::cpu.inst 0.066735 # Average percentage of cache occupancy
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system.cpu.icache.occ_percent::total 0.066735 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::cpu.inst 827 # number of ReadReq hits
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system.cpu.icache.ReadReq_hits::total 827 # number of ReadReq hits
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system.cpu.icache.demand_hits::cpu.inst 827 # number of demand (read+write) hits
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system.cpu.icache.demand_hits::total 827 # number of demand (read+write) hits
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system.cpu.icache.overall_hits::cpu.inst 827 # number of overall hits
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system.cpu.icache.overall_hits::total 827 # number of overall hits
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system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses
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system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses
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system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses
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system.cpu.icache.overall_misses::total 347 # number of overall misses
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system.cpu.icache.ReadReq_miss_latency::cpu.inst 19107000 # number of ReadReq miss cycles
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system.cpu.icache.ReadReq_miss_latency::total 19107000 # number of ReadReq miss cycles
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system.cpu.icache.demand_miss_latency::cpu.inst 19107000 # number of demand (read+write) miss cycles
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system.cpu.icache.demand_miss_latency::total 19107000 # number of demand (read+write) miss cycles
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system.cpu.icache.overall_miss_latency::cpu.inst 19107000 # number of overall miss cycles
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system.cpu.icache.overall_miss_latency::total 19107000 # number of overall miss cycles
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system.cpu.icache.ReadReq_accesses::cpu.inst 1174 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.ReadReq_accesses::total 1174 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.demand_accesses::cpu.inst 1174 # number of demand (read+write) accesses
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system.cpu.icache.demand_accesses::total 1174 # number of demand (read+write) accesses
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system.cpu.icache.overall_accesses::cpu.inst 1174 # number of overall (read+write) accesses
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system.cpu.icache.overall_accesses::total 1174 # number of overall (read+write) accesses
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system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295571 # miss rate for ReadReq accesses
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system.cpu.icache.demand_miss_rate::cpu.inst 0.295571 # miss rate for demand accesses
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system.cpu.icache.overall_miss_rate::cpu.inst 0.295571 # miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55063.400576 # average ReadReq miss latency
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system.cpu.icache.demand_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency
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system.cpu.icache.overall_avg_miss_latency::cpu.inst 55063.400576 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked_cycles::no_targets 106000 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets 35333.333333 # average number of cycles each access was blocked
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system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits
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system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
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system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits
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system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits
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system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits
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system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits
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system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
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system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
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system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
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system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
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system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
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system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
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system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15468000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_latency::total 15468000 # number of ReadReq MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15468000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.demand_mshr_miss_latency::total 15468000 # number of demand (read+write) MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15468000 # number of overall MSHR miss cycles
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system.cpu.icache.overall_mshr_miss_latency::total 15468000 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for ReadReq accesses
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system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for demand accesses
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system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247871 # mshr miss rate for overall accesses
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system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53154.639175 # average ReadReq mshr miss latency
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system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency
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system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53154.639175 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.replacements 0 # number of replacements
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system.cpu.dcache.tagsinuse 82.864730 # Cycle average of tags in use
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system.cpu.dcache.total_refs 1049 # Total number of references to valid blocks.
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system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks.
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system.cpu.dcache.avg_refs 7.770370 # Average number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.occ_blocks::cpu.data 82.864730 # Average occupied blocks per requestor
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system.cpu.dcache.occ_percent::cpu.data 0.020231 # Average percentage of cache occupancy
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system.cpu.dcache.occ_percent::total 0.020231 # Average percentage of cache occupancy
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system.cpu.dcache.ReadReq_hits::cpu.data 657 # number of ReadReq hits
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system.cpu.dcache.ReadReq_hits::total 657 # number of ReadReq hits
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system.cpu.dcache.WriteReq_hits::cpu.data 392 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 392 # number of WriteReq hits
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system.cpu.dcache.demand_hits::cpu.data 1049 # number of demand (read+write) hits
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system.cpu.dcache.demand_hits::total 1049 # number of demand (read+write) hits
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system.cpu.dcache.overall_hits::cpu.data 1049 # number of overall hits
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system.cpu.dcache.overall_hits::total 1049 # number of overall hits
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system.cpu.dcache.ReadReq_misses::cpu.data 59 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 59 # number of ReadReq misses
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system.cpu.dcache.WriteReq_misses::cpu.data 281 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 281 # number of WriteReq misses
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system.cpu.dcache.demand_misses::cpu.data 340 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 340 # number of demand (read+write) misses
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system.cpu.dcache.overall_misses::cpu.data 340 # number of overall misses
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system.cpu.dcache.overall_misses::total 340 # number of overall misses
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system.cpu.dcache.ReadReq_miss_latency::cpu.data 3291500 # number of ReadReq miss cycles
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system.cpu.dcache.ReadReq_miss_latency::total 3291500 # number of ReadReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::cpu.data 15458000 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_latency::total 15458000 # number of WriteReq miss cycles
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system.cpu.dcache.demand_miss_latency::cpu.data 18749500 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_latency::total 18749500 # number of demand (read+write) miss cycles
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system.cpu.dcache.overall_miss_latency::cpu.data 18749500 # number of overall miss cycles
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system.cpu.dcache.overall_miss_latency::total 18749500 # number of overall miss cycles
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system.cpu.dcache.ReadReq_accesses::cpu.data 716 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_accesses::total 716 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.demand_accesses::cpu.data 1389 # number of demand (read+write) accesses
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system.cpu.dcache.demand_accesses::total 1389 # number of demand (read+write) accesses
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system.cpu.dcache.overall_accesses::cpu.data 1389 # number of overall (read+write) accesses
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system.cpu.dcache.overall_accesses::total 1389 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082402 # miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417533 # miss rate for WriteReq accesses
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system.cpu.dcache.demand_miss_rate::cpu.data 0.244780 # miss rate for demand accesses
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system.cpu.dcache.overall_miss_rate::cpu.data 0.244780 # miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55788.135593 # average ReadReq miss latency
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system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55010.676157 # average WriteReq miss latency
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system.cpu.dcache.demand_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 55145.588235 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles::no_targets 2259500 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111 # average number of cycles each access was blocked
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
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system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::cpu.data 200 # number of WriteReq MSHR hits
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system.cpu.dcache.WriteReq_mshr_hits::total 200 # number of WriteReq MSHR hits
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system.cpu.dcache.demand_mshr_hits::cpu.data 205 # number of demand (read+write) MSHR hits
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system.cpu.dcache.demand_mshr_hits::total 205 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::cpu.data 205 # number of overall MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 205 # number of overall MSHR hits
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system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses
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system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses
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system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses
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system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses
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system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2866000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 2866000 # number of ReadReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4327500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_latency::total 4327500 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7193500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency::total 7193500 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7193500 # number of overall MSHR miss cycles
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system.cpu.dcache.overall_mshr_miss_latency::total 7193500 # number of overall MSHR miss cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075419 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for demand accesses
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system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097192 # mshr miss rate for overall accesses
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53074.074074 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53425.925926 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53285.185185 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 162.299655 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 136.188396 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 26.111259 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.004156 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.000797 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.004953 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 3 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 423 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15131000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 17917500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4230500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4230500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 15131000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 7017000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 22148000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 15131000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 7017000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 22148000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52356.401384 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52575.471698 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52356.401384 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52365.671642 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|