680 lines
77 KiB
Plaintext
680 lines
77 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.736384 # Number of seconds simulated
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sim_ticks 736384204000 # Number of ticks simulated
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final_tick 736384204000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 107029 # Simulator instruction rate (inst/s)
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host_op_rate 145759 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 56931535 # Simulator tick rate (ticks/s)
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host_mem_usage 233236 # Number of bytes of host memory used
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host_seconds 12934.56 # Real time elapsed on the host
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sim_insts 1384379033 # Number of instructions simulated
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sim_ops 1885333786 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read 94833536 # Number of bytes read from this memory
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system.physmem.bytes_inst_read 209216 # Number of instructions bytes read from this memory
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system.physmem.bytes_written 4230336 # Number of bytes written to this memory
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system.physmem.num_reads 1481774 # Number of read requests responded to by this memory
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system.physmem.num_writes 66099 # Number of write requests responded to by this memory
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system.physmem.num_other 0 # Number of other requests responded to by this memory
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system.physmem.bw_read 128782686 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read 284113 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write 5744740 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total 134527427 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 1411 # Number of system calls
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system.cpu.numCycles 1472768409 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 522739689 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 397666770 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 35592388 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 329507474 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 283194756 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 59112231 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 2837995 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 446610303 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 2608281266 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 522739689 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 342306987 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 709905843 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 224599686 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 101691904 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 2256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 28872 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 415462379 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 10233497 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 1441668699 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.553094 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.169508 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 731812218 50.76% 50.76% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 54028478 3.75% 54.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 112774395 7.82% 62.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 69112712 4.79% 67.13% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 82239849 5.70% 72.83% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 54732676 3.80% 76.63% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 35582945 2.47% 79.09% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 33403067 2.32% 81.41% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 267982359 18.59% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 1441668699 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.354937 # Number of branch fetches per cycle
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system.cpu.fetch.rate 1.771006 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 492629108 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 81861101 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 672684141 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 11080003 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 183414346 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 82040809 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 15532 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 3552890515 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 32736 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 183414346 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 530589836 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 29829797 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 3588754 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 644081795 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 50164171 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 3435316942 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 112 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 4205507 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 40993124 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.FullRegisterEvents 37 # Number of times there has been no free registers
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system.cpu.rename.RenamedOperands 3332970891 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 16270156364 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 15618651087 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 651505277 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 1993153599 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 1339817292 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 273156 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 268372 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 142469911 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 1057917040 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 579962844 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 32519670 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 39211966 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 3198933227 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 269334 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 2725360235 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 26814777 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 1313459573 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 3048227605 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 58004 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 1441668699 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 1.890421 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.914096 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 524357405 36.37% 36.37% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 197522511 13.70% 50.07% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 215009168 14.91% 64.99% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 179008270 12.42% 77.40% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 156604882 10.86% 88.27% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 103164450 7.16% 95.42% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 49203607 3.41% 98.83% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 11056090 0.77% 99.60% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 5742316 0.40% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 1441668699 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 2118699 2.21% 2.21% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 23832 0.02% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.23% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 56614089 59.02% 61.26% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 37163288 38.74% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 1266333715 46.46% 46.46% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 11230148 0.41% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.88% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.93% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.93% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 6876563 0.25% 47.18% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 5503497 0.20% 47.38% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 38 0.00% 47.38% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 23211520 0.85% 48.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.23% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 900219934 33.03% 81.26% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 510609530 18.74% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 2725360235 # Type of FU issued
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system.cpu.iq.rate 1.850502 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 95919908 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.035195 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 6880679936 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 4410033557 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 2496172626 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 134443918 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 102684223 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 60255652 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 2752299483 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 68980660 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 71230775 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 426528171 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 281369 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 1323673 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 302965860 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 92 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 26 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 183414346 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 16249953 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 1608700 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 3199274316 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 7370103 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 1057917040 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 579962844 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 258370 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 1607775 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 215 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 1323673 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 37204877 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 8928711 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 46133588 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 2624820303 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 845791055 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 100539932 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 71755 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 1327328363 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 362158100 # Number of branches executed
|
|
system.cpu.iew.exec_stores 481537308 # Number of stores executed
|
|
system.cpu.iew.exec_rate 1.782236 # Inst execution rate
|
|
system.cpu.iew.wb_sent 2584846968 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 2556428278 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 1474733618 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 2760579704 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 1.735798 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.534212 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions
|
|
system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 1313929852 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 41115032 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 1258254355 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 1.498381 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.211057 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 578553729 45.98% 45.98% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 316892144 25.19% 71.17% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 101707631 8.08% 79.25% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 79187361 6.29% 85.54% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 52970249 4.21% 89.75% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 24190672 1.92% 91.67% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 17058373 1.36% 93.03% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 9262849 0.74% 93.77% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 78431347 6.23% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 1258254355 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 1384390049 # Number of instructions committed
|
|
system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 908385853 # Number of memory references committed
|
|
system.cpu.commit.loads 631388869 # Number of loads committed
|
|
system.cpu.commit.membars 9986 # Number of memory barriers committed
|
|
system.cpu.commit.branches 291350232 # Number of branches committed
|
|
system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 1653705623 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 41577833 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 78431347 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 4379079317 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 6581974646 # The number of ROB writes
|
|
system.cpu.timesIdled 1328714 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 31099710 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 1384379033 # Number of Instructions Simulated
|
|
system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated
|
|
system.cpu.cpi 1.063848 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 1.063848 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.939984 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.939984 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 12935043618 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 2425775909 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 71439411 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 51051626 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 4084910091 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 13776276 # number of misc regfile writes
|
|
system.cpu.icache.replacements 28501 # number of replacements
|
|
system.cpu.icache.tagsinuse 1662.292931 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 415426412 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 30198 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 13756.752500 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1662.292931 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.811666 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.811666 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 415426419 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 415426419 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 415426419 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 415426419 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 415426419 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 415426419 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 35960 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 35960 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 35960 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 35960 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 35960 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 35960 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 314726500 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 314726500 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 314726500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 314726500 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 314726500 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 314726500 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 415462379 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 415462379 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 415462379 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 415462379 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 415462379 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 415462379 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8752.127364 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8752.127364 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 780 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 780 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 780 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 780 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 780 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 780 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 35180 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 35180 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 35180 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 35180 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 35180 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 35180 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 188682500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 188682500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 188682500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 188682500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 188682500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 188682500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5363.345651 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5363.345651 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 1532334 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4094.808393 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 1033081236 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 1536430 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 672.390695 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 312649000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4094.808393 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.999709 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.999709 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 756924525 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 756924525 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 276114347 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 276114347 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 12957 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 12957 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 11669 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 11669 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1033038872 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1033038872 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1033038872 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1033038872 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 2432909 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 2432909 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 821331 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 821331 # number of WriteReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::cpu.data 3 # number of StoreCondReq misses
|
|
system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 3254240 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 3254240 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 3254240 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 3254240 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 81657017500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 81657017500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 28588903000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 28588903000 # number of WriteReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 108000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.LoadLockedReq_miss_latency::total 108000 # number of LoadLockedReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 16500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.StoreCondReq_miss_latency::total 16500 # number of StoreCondReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 110245920500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 110245920500 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 110245920500 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 110245920500 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 759357434 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 759357434 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12960 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 12960 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 11672 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 11672 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 1036293112 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 1036293112 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 1036293112 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 1036293112 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003204 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002966 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000231 # miss rate for LoadLockedReq accesses
|
|
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000257 # miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.003140 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.003140 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33563.531353 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34808.016500 # average WriteReq miss latency
|
|
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36000 # average LoadLockedReq miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 5500 # average StoreCondReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 33877.624422 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 80000 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 106562 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 106562 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 969189 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 969189 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743643 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 743643 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1712832 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1712832 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1712832 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1712832 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1463720 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1463720 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77688 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 77688 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 3 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1541408 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1541408 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1541408 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1541408 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50029308500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 50029308500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2504136000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 2504136000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 7500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 7500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52533444500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 52533444500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52533444500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 52533444500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001928 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000281 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000257 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001487 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34179.562006 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32233.240655 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 2500 # average StoreCondReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34081.466101 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 1480213 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 31972.758917 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 86473 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 1512931 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.057156 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 2964.503438 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 60.794216 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 28947.461262 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.090469 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.001855 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.883406 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.975731 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 26928 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 51269 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 78197 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 106562 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 106562 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 6630 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 6630 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 26928 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 57899 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 84827 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 26928 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 57899 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 84827 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 3274 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 1412451 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 1415725 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 4973 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 4973 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 66080 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 66080 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 3274 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 1478531 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 1481805 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 3274 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 1478531 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 1481805 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 112237000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48455418000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 48567655000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2252377500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 2252377500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 112237000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 50707795500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 50820032500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 112237000 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 50707795500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 50820032500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 30202 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1463720 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 1493922 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 106562 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 106562 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4978 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 4978 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 72710 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 72710 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 30202 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1536430 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 1566632 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 30202 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1536430 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 1566632 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108403 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.964973 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.998996 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908816 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.108403 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.962316 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108403 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.962316 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34281.307269 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34305.910789 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34085.615920 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34281.307269 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34296.065148 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34281.307269 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34296.065148 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 66099 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 26 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 31 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 31 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 31 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3269 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1412425 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 1415694 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4973 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 4973 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66080 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 66080 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 3269 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 1478505 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 1481774 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 3269 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 1478505 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 1481774 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 101602500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43882479500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43984082000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 154163000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 154163000 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048540000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048540000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101602500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45931019500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 46032622000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101602500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45931019500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 46032622000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964956 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.998996 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908816 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108238 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962299 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.605690 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31068.891800 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.907990 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.605690 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.853345 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|