Andreas Hansson 28a7cea2b3 config: Add XOR hashing to the DRAM channel interleaving ... This patch uses the recently added XOR hashing capabilities for the DRAM channel interleaving. This avoids channel biasing due to strided access patterns.		2015-02-03 14:25:55 -05:00
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boot	rcs scripts: remove bbench.rcS	2013-04-02 12:46:49 -04:00
common	config: Add XOR hashing to the DRAM channel interleaving	2015-02-03 14:25:55 -05:00
dram	mem: Rename Bus to XBar to better reflect its behaviour	2014-09-20 17:18:32 -04:00
example	scons: Do not build the InOrderCPU	2015-01-20 08:12:45 -05:00
ruby	config, ruby: connect dma to network	2015-01-20 14:15:28 -06:00
splash2	mem: Rename Bus to XBar to better reflect its behaviour	2014-09-20 17:18:32 -04:00
topologies	config: topologies: slight code refactor	2014-02-23 19:16:15 -06:00