config: Add XOR hashing to the DRAM channel interleaving
This patch uses the recently added XOR hashing capabilities for the DRAM channel interleaving. This avoids channel biasing due to strided access patterns.
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1 changed files with 9 additions and 0 deletions
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@ -137,6 +137,13 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
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import math
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intlv_low_bit = int(math.log(intlv_size, 2))
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# Use basic hashing for the channel selection, and preferably use
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# the lower tag bits from the last level cache. As we do not know
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# the details of the caches here, make an educated guess. 4 MByte
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# 4-way associative with 64 byte cache lines is 6 offset bits and
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# 14 index bits.
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xor_low_bit = 20
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# Create an instance so we can figure out the address
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# mapping and row-buffer size
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ctrl = cls()
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@ -165,6 +172,8 @@ def create_mem_ctrl(cls, r, i, nbr_mem_ctrls, intlv_bits, intlv_size):
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ctrl.range = m5.objects.AddrRange(r.start, size = r.size(),
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intlvHighBit = \
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intlv_low_bit + intlv_bits - 1,
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xorHighBit = \
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xor_low_bit + intlv_bits - 1,
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intlvBits = intlv_bits,
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intlvMatch = i)
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return ctrl
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