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gem5/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
Steve Reinhardt 10e6450120 test: update stats 
Update stats for recent changes.  Mostly minor changes
in register access stats due to addition of new cc
register type and slightly different (and more accurate)
classification of int vs. fp register accesses.
2013-10-16 10:44:12 -04:00

1680 lines
32 KiB
INI
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[root]
type=Root
children=system
full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxAlphaSystem
children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
cache_line_size=64
clk_domain=system.clk_domain
console=/dist/m5/system/binaries/console
init_param=0
kernel=/dist/m5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
mem_ranges=0:134217727
memories=system.physmem
num_work_ids=16
pal=/dist/m5/system/binaries/ts_osfpal
readfile=tests/halt.sh
symbolfile=
system_rev=1024
system_type=34
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.bridge]
type=Bridge
clk_domain=system.clk_domain
delay=50000
ranges=8796093022208:18446744073709551615
req_size=16
resp_size=16
master=system.iobus.slave[0]
slave=system.membus.master[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
voltage_domain=system.voltage_domain
[system.cpu0]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu0.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=0
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu0.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu0.interrupts
isa=system.cpu0.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu0.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
[system.cpu0.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu0.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu0.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.dcache_port
mem_side=system.toL2Bus.slave[1]
[system.cpu0.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu0.dtb]
type=AlphaTLB
size=64
[system.cpu0.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8
[system.cpu0.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu0.fuPool.FUList0.opList
[system.cpu0.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu0.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1
[system.cpu0.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu0.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu0.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2
[system.cpu0.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu0.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu0.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu0.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2
[system.cpu0.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu0.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu0.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu0.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu0.fuPool.FUList4.opList
[system.cpu0.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19
[system.cpu0.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu0.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu0.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu0.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu0.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu0.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu0.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu0.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu0.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu0.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu0.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu0.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu0.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu0.fuPool.FUList6.opList
[system.cpu0.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1
[system.cpu0.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu0.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu0.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu0.fuPool.FUList8.opList
[system.cpu0.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu0.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu0.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.slave[0]
[system.cpu0.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu0.interrupts]
type=AlphaInterrupts
[system.cpu0.isa]
type=AlphaISA
[system.cpu0.itb]
type=AlphaTLB
size=48
[system.cpu0.tracer]
type=ExeTracer
[system.cpu1]
type=DerivO3CPU
children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
LFSTSize=1024
LQEntries=32
LSQCheckLoads=true
LSQDepCheckShift=4
SQEntries=32
SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu1.branchPred
cachePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
commitToFetchDelay=1
commitToIEWDelay=1
commitToRenameDelay=1
commitWidth=8
cpu_id=1
decodeToFetchDelay=1
decodeToRenameDelay=1
decodeWidth=8
dispatchWidth=8
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
fetchToDecodeDelay=1
fetchTrapLatency=1
fetchWidth=8
forwardComSize=5
fuPool=system.cpu1.fuPool
function_trace=false
function_trace_start=0
iewToCommitDelay=1
iewToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
interrupts=system.cpu1.interrupts
isa=system.cpu1.isa
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
needsTSO=false
numIQEntries=64
numPhysCCRegs=0
numPhysFloatRegs=256
numPhysIntRegs=256
numROBEntries=192
numRobs=1
numThreads=1
profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
renameToIEWDelay=2
renameToROBDelay=1
renameWidth=8
simpoint_start_insts=
smtCommitPolicy=RoundRobin
smtFetchPolicy=SingleThread
smtIQPolicy=Partitioned
smtIQThreshold=100
smtLSQPolicy=Partitioned
smtLSQThreshold=100
smtNumFetchingThreads=1
smtROBPolicy=Partitioned
smtROBThreshold=100
squashWidth=8
store_set_clear_period=250000
switched_out=false
system=system
tracer=system.cpu1.tracer
trapLatency=13
wbDepth=1
wbWidth=8
workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
[system.cpu1.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu1.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=4
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu1.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.dcache_port
mem_side=system.toL2Bus.slave[3]
[system.cpu1.dcache.tags]
type=LRU
assoc=4
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu1.dtb]
type=AlphaTLB
size=64
[system.cpu1.fuPool]
type=FUPool
children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8
[system.cpu1.fuPool.FUList0]
type=FUDesc
children=opList
count=6
opList=system.cpu1.fuPool.FUList0.opList
[system.cpu1.fuPool.FUList0.opList]
type=OpDesc
issueLat=1
opClass=IntAlu
opLat=1
[system.cpu1.fuPool.FUList1]
type=FUDesc
children=opList0 opList1
count=2
opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1
[system.cpu1.fuPool.FUList1.opList0]
type=OpDesc
issueLat=1
opClass=IntMult
opLat=3
[system.cpu1.fuPool.FUList1.opList1]
type=OpDesc
issueLat=19
opClass=IntDiv
opLat=20
[system.cpu1.fuPool.FUList2]
type=FUDesc
children=opList0 opList1 opList2
count=4
opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2
[system.cpu1.fuPool.FUList2.opList0]
type=OpDesc
issueLat=1
opClass=FloatAdd
opLat=2
[system.cpu1.fuPool.FUList2.opList1]
type=OpDesc
issueLat=1
opClass=FloatCmp
opLat=2
[system.cpu1.fuPool.FUList2.opList2]
type=OpDesc
issueLat=1
opClass=FloatCvt
opLat=2
[system.cpu1.fuPool.FUList3]
type=FUDesc
children=opList0 opList1 opList2
count=2
opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2
[system.cpu1.fuPool.FUList3.opList0]
type=OpDesc
issueLat=1
opClass=FloatMult
opLat=4
[system.cpu1.fuPool.FUList3.opList1]
type=OpDesc
issueLat=12
opClass=FloatDiv
opLat=12
[system.cpu1.fuPool.FUList3.opList2]
type=OpDesc
issueLat=24
opClass=FloatSqrt
opLat=24
[system.cpu1.fuPool.FUList4]
type=FUDesc
children=opList
count=0
opList=system.cpu1.fuPool.FUList4.opList
[system.cpu1.fuPool.FUList4.opList]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
count=4
opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19
[system.cpu1.fuPool.FUList5.opList00]
type=OpDesc
issueLat=1
opClass=SimdAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList01]
type=OpDesc
issueLat=1
opClass=SimdAddAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList02]
type=OpDesc
issueLat=1
opClass=SimdAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList03]
type=OpDesc
issueLat=1
opClass=SimdCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList04]
type=OpDesc
issueLat=1
opClass=SimdCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList05]
type=OpDesc
issueLat=1
opClass=SimdMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList06]
type=OpDesc
issueLat=1
opClass=SimdMult
opLat=1
[system.cpu1.fuPool.FUList5.opList07]
type=OpDesc
issueLat=1
opClass=SimdMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList08]
type=OpDesc
issueLat=1
opClass=SimdShift
opLat=1
[system.cpu1.fuPool.FUList5.opList09]
type=OpDesc
issueLat=1
opClass=SimdShiftAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList10]
type=OpDesc
issueLat=1
opClass=SimdSqrt
opLat=1
[system.cpu1.fuPool.FUList5.opList11]
type=OpDesc
issueLat=1
opClass=SimdFloatAdd
opLat=1
[system.cpu1.fuPool.FUList5.opList12]
type=OpDesc
issueLat=1
opClass=SimdFloatAlu
opLat=1
[system.cpu1.fuPool.FUList5.opList13]
type=OpDesc
issueLat=1
opClass=SimdFloatCmp
opLat=1
[system.cpu1.fuPool.FUList5.opList14]
type=OpDesc
issueLat=1
opClass=SimdFloatCvt
opLat=1
[system.cpu1.fuPool.FUList5.opList15]
type=OpDesc
issueLat=1
opClass=SimdFloatDiv
opLat=1
[system.cpu1.fuPool.FUList5.opList16]
type=OpDesc
issueLat=1
opClass=SimdFloatMisc
opLat=1
[system.cpu1.fuPool.FUList5.opList17]
type=OpDesc
issueLat=1
opClass=SimdFloatMult
opLat=1
[system.cpu1.fuPool.FUList5.opList18]
type=OpDesc
issueLat=1
opClass=SimdFloatMultAcc
opLat=1
[system.cpu1.fuPool.FUList5.opList19]
type=OpDesc
issueLat=1
opClass=SimdFloatSqrt
opLat=1
[system.cpu1.fuPool.FUList6]
type=FUDesc
children=opList
count=0
opList=system.cpu1.fuPool.FUList6.opList
[system.cpu1.fuPool.FUList6.opList]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList7]
type=FUDesc
children=opList0 opList1
count=4
opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1
[system.cpu1.fuPool.FUList7.opList0]
type=OpDesc
issueLat=1
opClass=MemRead
opLat=1
[system.cpu1.fuPool.FUList7.opList1]
type=OpDesc
issueLat=1
opClass=MemWrite
opLat=1
[system.cpu1.fuPool.FUList8]
type=FUDesc
children=opList
count=1
opList=system.cpu1.fuPool.FUList8.opList
[system.cpu1.fuPool.FUList8.opList]
type=OpDesc
issueLat=3
opClass=IprAccess
opLat=3
[system.cpu1.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=1
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
size=32768
system=system
tags=system.cpu1.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.slave[2]
[system.cpu1.icache.tags]
type=LRU
assoc=1
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=2
size=32768
[system.cpu1.interrupts]
type=AlphaInterrupts
[system.cpu1.isa]
type=AlphaISA
[system.cpu1.itb]
type=AlphaTLB
size=48
[system.cpu1.tracer]
type=ExeTracer
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
voltage_domain=system.voltage_domain
[system.disk0]
type=IdeDisk
children=image
delay=1000000
driveID=master
image=system.disk0.image
[system.disk0.image]
type=CowDiskImage
children=child
child=system.disk0.image.child
image_file=
read_only=false
table_size=65536
[system.disk0.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
type=IdeDisk
children=image
delay=1000000
driveID=master
image=system.disk2.image
[system.disk2.image]
type=CowDiskImage
children=child
child=system.disk2.image.child
image_file=
read_only=false
table_size=65536
[system.disk2.image.child]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
type=IntrControl
sys=system
[system.iobus]
type=NoncoherentBus
clk_domain=system.clk_domain
header_cycles=1
use_default_range=true
width=8
default=system.tsunami.pciconfig.pio
master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
[system.iocache]
type=BaseCache
children=tags
addr_ranges=0:134217727
assoc=8
clk_domain=system.clk_domain
forward_snoops=false
hit_latency=50
is_top_level=true
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=50
size=1024
system=system
tags=system.iocache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.iobus.master[29]
mem_side=system.membus.slave[2]
[system.iocache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.clk_domain
hit_latency=50
size=1024
[system.l2c]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
size=4194304
system=system
tags=system.l2c.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.l2c.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
hit_latency=20
size=4194304
[system.membus]
type=CoherentBus
children=badaddr_responder
clk_domain=system.clk_domain
header_cycles=1
system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
master=system.bridge.slave system.physmem.port
slave=system.system_port system.l2c.mem_side system.iocache.mem_side
[system.membus.badaddr_responder]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=0
pio_latency=100000
pio_size=8
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.membus.default
[system.physmem]
type=SimpleDRAM
activation_limit=4
addr_mapping=RaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
in_addr_map=true
mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCL=13750
tRCD=13750
tREFI=7800000
tRFC=300000
tRP=13750
tWTR=7500
tXAW=40000
write_buffer_size=32
write_thresh_perc=70
port=system.membus.master[1]
[system.simple_disk]
type=SimpleDisk
children=disk
disk=system.simple_disk.disk
system=system
[system.simple_disk.disk]
type=RawDiskImage
image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
type=Terminal
intr_control=system.intrctrl
number=0
output=true
port=3456
[system.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
header_cycles=1
system=system
use_default_range=false
width=8
master=system.l2c.cpu_side
slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side
[system.tsunami]
type=Tsunami
children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
intrctrl=system.intrctrl
system=system
[system.tsunami.backdoor]
type=AlphaBackdoor
clk_domain=system.clk_domain
cpu=system.cpu0
disk=system.simple_disk
pio_addr=8804682956800
pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
pio=system.iobus.master[24]
[system.tsunami.cchip]
type=TsunamiCChip
clk_domain=system.clk_domain
pio_addr=8803072344064
pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[0]
[system.tsunami.ethernet]
type=NSGigE
BAR0=1
BAR0LegacyIO=false
BAR0Size=256
BAR1=0
BAR1LegacyIO=false
BAR1Size=4096
BAR2=0
BAR2LegacyIO=false
BAR2Size=0
BAR3=0
BAR3LegacyIO=false
BAR3Size=0
BAR4=0
BAR4LegacyIO=false
BAR4Size=0
BAR5=0
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CardbusCIS=0
ClassCode=2
Command=0
DeviceID=34
ExpansionROM=0
HeaderType=0
InterruptLine=30
InterruptPin=1
LatencyTimer=0
MaximumLatency=52
MinimumGrant=176
ProgIF=0
Revision=0
Status=656
SubClassCode=0
SubsystemID=0
SubsystemVendorID=0
VendorID=4107
clk_domain=system.clk_domain
config_latency=20000
dma_data_free=false
dma_desc_free=false
dma_no_allocate=true
dma_read_delay=0
dma_read_factor=0
dma_write_delay=0
dma_write_factor=0
hardware_address=00:90:00:00:00:01
intr_delay=10000000
pci_bus=0
pci_dev=1
pci_func=0
pio_latency=30000
platform=system.tsunami
rss=false
rx_delay=1000000
rx_fifo_size=524288
rx_filter=true
rx_thread=false
system=system
tx_delay=1000000
tx_fifo_size=524288
tx_thread=false
config=system.iobus.master[28]
dma=system.iobus.slave[2]
pio=system.iobus.master[27]
[system.tsunami.fake_OROM]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8796093677568
pio_latency=100000
pio_size=393216
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[8]
[system.tsunami.fake_ata0]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848432
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[19]
[system.tsunami.fake_ata1]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848304
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[20]
[system.tsunami.fake_pnp_addr]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848569
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[9]
[system.tsunami.fake_pnp_read0]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848451
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[11]
[system.tsunami.fake_pnp_read1]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848515
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[12]
[system.tsunami.fake_pnp_read2]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848579
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[13]
[system.tsunami.fake_pnp_read3]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848643
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[14]
[system.tsunami.fake_pnp_read4]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848707
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[15]
[system.tsunami.fake_pnp_read5]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848771
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[16]
[system.tsunami.fake_pnp_read6]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848835
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[17]
[system.tsunami.fake_pnp_read7]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848899
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[18]
[system.tsunami.fake_pnp_write]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615850617
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[10]
[system.tsunami.fake_ppc]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848891
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[7]
[system.tsunami.fake_sm_chip]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848816
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[2]
[system.tsunami.fake_uart1]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848696
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[3]
[system.tsunami.fake_uart2]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848936
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[4]
[system.tsunami.fake_uart3]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848680
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[5]
[system.tsunami.fake_uart4]
type=IsaFake
clk_domain=system.clk_domain
fake_mem=false
pio_addr=8804615848944
pio_latency=100000
pio_size=8
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ret_data64=18446744073709551615
ret_data8=255
system=system
update_data=false
warn_access=
pio=system.iobus.master[6]
[system.tsunami.fb]
type=BadDevice
clk_domain=system.clk_domain
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=100000
system=system
pio=system.iobus.master[21]
[system.tsunami.ide]
type=IdeController
BAR0=1
BAR0LegacyIO=false
BAR0Size=8
BAR1=1
BAR1LegacyIO=false
BAR1Size=4
BAR2=1
BAR2LegacyIO=false
BAR2Size=8
BAR3=1
BAR3LegacyIO=false
BAR3Size=4
BAR4=1
BAR4LegacyIO=false
BAR4Size=16
BAR5=1
BAR5LegacyIO=false
BAR5Size=0
BIST=0
CacheLineSize=0
CardbusCIS=0
ClassCode=1
Command=0
DeviceID=28945
ExpansionROM=0
HeaderType=0
InterruptLine=31
InterruptPin=1
LatencyTimer=0
MaximumLatency=0
MinimumGrant=0
ProgIF=133
Revision=0
Status=640
SubClassCode=1
SubsystemID=0
SubsystemVendorID=0
VendorID=32902
clk_domain=system.clk_domain
config_latency=20000
ctrl_offset=0
disks=system.disk0 system.disk2
io_shift=0
pci_bus=0
pci_dev=0
pci_func=0
pio_latency=30000
platform=system.tsunami
system=system
config=system.iobus.master[26]
dma=system.iobus.slave[1]
pio=system.iobus.master[25]
[system.tsunami.io]
type=TsunamiIO
clk_domain=system.clk_domain
frequency=976562500
pio_addr=8804615847936
pio_latency=100000
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
year_is_bcd=false
pio=system.iobus.master[22]
[system.tsunami.pchip]
type=TsunamiPChip
clk_domain=system.clk_domain
pio_addr=8802535473152
pio_latency=100000
system=system
tsunami=system.tsunami
pio=system.iobus.master[1]
[system.tsunami.pciconfig]
type=PciConfigAll
bus=0
clk_domain=system.clk_domain
pio_addr=0
pio_latency=30000
platform=system.tsunami
size=16777216
system=system
pio=system.iobus.default
[system.tsunami.uart]
type=Uart8250
clk_domain=system.clk_domain
pio_addr=8804615848952
pio_latency=100000
platform=system.tsunami
system=system
terminal=system.terminal
pio=system.iobus.master[23]
[system.voltage_domain]
type=VoltageDomain
voltage=1.000000
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