233 lines
7.3 KiB
C++
233 lines
7.3 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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// Todo:
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// Fix up trap and barrier handling.
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// May want to have different statuses to differentiate the different stall
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// conditions.
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#ifndef __CPU_O3_CPU_SIMPLE_RENAME_HH__
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#define __CPU_O3_CPU_SIMPLE_RENAME_HH__
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#include <list>
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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// Will need rename maps for both the int reg file and fp reg file.
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// Or change rename map class to handle both. (RegFile handles both.)
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template<class Impl>
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class SimpleRename
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{
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public:
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// Typedefs from the Impl.
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typedef typename Impl::CPUPol CPUPol;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef typename Impl::FullCPU FullCPU;
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typedef typename Impl::Params Params;
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typedef typename CPUPol::FetchStruct FetchStruct;
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typedef typename CPUPol::DecodeStruct DecodeStruct;
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typedef typename CPUPol::RenameStruct RenameStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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// Typedefs from the CPUPol
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typedef typename CPUPol::FreeList FreeList;
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typedef typename CPUPol::RenameMap RenameMap;
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// Typedefs from the ISA.
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typedef TheISA::RegIndex RegIndex;
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public:
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// Rename will block if ROB becomes full or issue queue becomes full,
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// or there are no free registers to rename to.
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// Only case where rename squashes is if IEW squashes.
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enum Status {
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Running,
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Idle,
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Squashing,
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Blocked,
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Unblocking,
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BarrierStall
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};
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private:
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Status _status;
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public:
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SimpleRename(Params ¶ms);
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void regStats();
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void setCPU(FullCPU *cpu_ptr);
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void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
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void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
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void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
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void setRenameMap(RenameMap *rm_ptr);
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void setFreeList(FreeList *fl_ptr);
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void dumpHistory();
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void tick();
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void rename();
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void squash();
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private:
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void block();
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inline void unblock();
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void doSquash();
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void removeFromHistory(InstSeqNum inst_seq_num);
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inline void renameSrcRegs(DynInstPtr &inst);
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inline void renameDestRegs(DynInstPtr &inst);
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inline int calcFreeROBEntries();
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inline int calcFreeIQEntries();
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/** Holds the previous information for each rename.
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* Note that often times the inst may have been deleted, so only access
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* the pointer for the address and do not dereference it.
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*/
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struct RenameHistory {
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RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
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PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
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: instSeqNum(_instSeqNum), archReg(_archReg),
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newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
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placeHolder(false)
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{
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}
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/** Constructor used specifically for cases where a place holder
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* rename history entry is being made.
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*/
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RenameHistory(InstSeqNum _instSeqNum)
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: instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
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prevPhysReg(0), placeHolder(true)
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{
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}
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InstSeqNum instSeqNum;
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RegIndex archReg;
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PhysRegIndex newPhysReg;
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PhysRegIndex prevPhysReg;
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bool placeHolder;
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};
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std::list<RenameHistory> historyBuffer;
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/** CPU interface. */
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FullCPU *cpu;
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// Interfaces to objects outside of rename.
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/** Time buffer interface. */
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TimeBuffer<TimeStruct> *timeBuffer;
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/** Wire to get IEW's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromIEW;
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/** Wire to get commit's output from backwards time buffer. */
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typename TimeBuffer<TimeStruct>::wire fromCommit;
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/** Wire to write infromation heading to previous stages. */
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// Might not be the best name as not only decode will read it.
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typename TimeBuffer<TimeStruct>::wire toDecode;
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/** Rename instruction queue. */
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TimeBuffer<RenameStruct> *renameQueue;
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/** Wire to write any information heading to IEW. */
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typename TimeBuffer<RenameStruct>::wire toIEW;
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/** Decode instruction queue interface. */
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TimeBuffer<DecodeStruct> *decodeQueue;
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/** Wire to get decode's output from decode queue. */
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typename TimeBuffer<DecodeStruct>::wire fromDecode;
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/** Skid buffer between rename and decode. */
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std::queue<DecodeStruct> skidBuffer;
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/** Rename map interface. */
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SimpleRenameMap *renameMap;
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/** Free list interface. */
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FreeList *freeList;
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/** Delay between iew and rename, in ticks. */
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int iewToRenameDelay;
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/** Delay between decode and rename, in ticks. */
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int decodeToRenameDelay;
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/** Delay between commit and rename, in ticks. */
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unsigned commitToRenameDelay;
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/** Rename width, in instructions. */
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unsigned renameWidth;
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/** Commit width, in instructions. Used so rename knows how many
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* instructions might have freed registers in the previous cycle.
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*/
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unsigned commitWidth;
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/** The instruction that rename is currently on. It needs to have
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* persistent state so that when a stall occurs in the middle of a
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* group of instructions, it can restart at the proper instruction.
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*/
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unsigned numInst;
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Stats::Scalar<> renameSquashCycles;
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Stats::Scalar<> renameIdleCycles;
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Stats::Scalar<> renameBlockCycles;
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Stats::Scalar<> renameUnblockCycles;
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Stats::Scalar<> renameRenamedInsts;
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Stats::Scalar<> renameSquashedInsts;
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Stats::Scalar<> renameROBFullEvents;
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Stats::Scalar<> renameIQFullEvents;
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Stats::Scalar<> renameFullRegistersEvents;
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Stats::Scalar<> renameRenamedOperands;
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Stats::Scalar<> renameRenameLookups;
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Stats::Scalar<> renameHBPlaceHolders;
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Stats::Scalar<> renameCommittedMaps;
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Stats::Scalar<> renameUndoneMaps;
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Stats::Scalar<> renameValidUndoneMaps;
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};
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#endif // __CPU_O3_CPU_SIMPLE_RENAME_HH__
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