Steve Reinhardt e57ab463cf mem: remove redundant test in in Cache::recvTimingResp() ... For some reason we were checking mshr->hasTargets() even though we had already called mshr->getTarget() unconditionally earlier in the same function (which asserts if there are no targets). Get rid of this useless check, and while we're at it get rid of the redundant call to mshr->getTarget(), since we still have the value saved in a local var.		2015-02-11 10:48:53 -08:00
..
arch	arm: Share a port for the two table walker objects	2015-03-02 04:00:42 -05:00
base	base: Add compiler macros to add deprecation warnings	2015-02-11 10:23:24 -05:00
cpu	cpu: o3: another assert instead of check	2015-03-09 09:39:08 -05:00
dev	dev, arm: Clean up PL011 and rewrite interrupt handling	2015-03-02 04:00:44 -05:00
doc	cpu: `Minor' in-order CPU model	2014-07-23 16:09:04 -05:00
doxygen	MEM: Put memory system document into doxygen	2012-09-25 11:49:41 -05:00
kern	misc: Move AddrRangeList from port.hh to addr_range.hh	2014-10-16 05:49:59 -04:00
mem	mem: remove redundant test in in Cache::recvTimingResp()	2015-02-11 10:48:53 -08:00
proto	cpu: add support for outputing a protobuf formatted CPU trace	2015-02-16 03:32:38 -05:00
python	base: Add XOR-based hashed address interleaving	2015-02-03 14:25:54 -05:00
sim	mem: Split port retry for all different packet classes	2015-03-02 04:00:35 -05:00
unittest	test: Add a unittest for the BitUnion types.	2015-01-07 00:34:40 -08:00
Doxyfile	Doxygen: Update the version of the Doxyfile	2012-10-11 06:38:42 -04:00
SConscript	base: Add compiler macros to add deprecation warnings	2015-02-11 10:23:24 -05:00