3fea59e162
This patch moves send/recvTiming and send/recvTimingSnoop from the Port base class to the MasterPort and SlavePort, and also splits them into separate member functions for requests and responses: send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, send/recvTimingSnoopResp. A master port sends requests and receives responses, and also receives snoop requests and sends snoop responses. A slave port has the reciprocal behaviour as it receives requests and sends responses, and sends snoop requests and receives snoop responses. For all MemObjects that have only master ports or slave ports (but not both), e.g. a CPU, or a PIO device, this patch merely adds more clarity to what kind of access is taking place. For example, a CPU port used to call sendTiming, and will now call sendTimingReq. Similarly, a response previously came back through recvTiming, which is now recvTimingResp. For the modules that have both master and slave ports, e.g. the bus, the behaviour was previously relying on branches based on pkt->isRequest(), and this is now replaced with a direct call to the apprioriate member function depending on the type of access. Please note that send/recvRetry is still shared by all the timing accessors and remains in the Port base class for now (to maintain the current bus functionality and avoid changing the statistics of all regressions). The packet queue is split into a MasterPort and SlavePort version to facilitate the use of the new timing accessors. All uses of the PacketQueue are updated accordingly. With this patch, the type of packet (request or response) is now well defined for each type of access, and asserts on pkt->isRequest() and pkt->isResponse() are now moved to the appropriate send member functions. It is also worth noting that sendTimingSnoopReq no longer returns a boolean, as the semantics do not alow snoop requests to be rejected or stalled. All these assumptions are now excplicitly part of the port interface itself.
1297 lines
37 KiB
C++
1297 lines
37 KiB
C++
/*
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* Copyright (c) 2010-2011 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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*/
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#include "arch/generic/debugfaults.hh"
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#include "arch/locked_mem.hh"
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#include "base/str.hh"
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#include "config/the_isa.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/o3/lsq.hh"
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#include "cpu/o3/lsq_unit.hh"
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#include "debug/Activity.hh"
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#include "debug/IEW.hh"
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#include "debug/LSQUnit.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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template<class Impl>
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LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
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LSQUnit *lsq_ptr)
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: Event(Default_Pri, AutoDelete),
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inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
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{
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}
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template<class Impl>
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void
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LSQUnit<Impl>::WritebackEvent::process()
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{
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if (!lsqPtr->isSwitchedOut()) {
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lsqPtr->writeback(inst, pkt);
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}
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if (pkt->senderState)
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delete pkt->senderState;
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delete pkt->req;
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delete pkt;
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}
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template<class Impl>
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const char *
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LSQUnit<Impl>::WritebackEvent::description() const
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{
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return "Store writeback";
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}
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template<class Impl>
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void
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LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
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{
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LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
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DynInstPtr inst = state->inst;
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DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum);
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DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum);
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//iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
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assert(!pkt->wasNacked());
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// If this is a split access, wait until all packets are received.
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if (TheISA::HasUnalignedMemAcc && !state->complete()) {
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delete pkt->req;
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delete pkt;
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return;
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}
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if (isSwitchedOut() || inst->isSquashed()) {
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iewStage->decrWb(inst->seqNum);
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} else {
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if (!state->noWB) {
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if (!TheISA::HasUnalignedMemAcc || !state->isSplit ||
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!state->isLoad) {
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writeback(inst, pkt);
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} else {
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writeback(inst, state->mainPkt);
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}
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}
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if (inst->isStore()) {
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completeStore(state->idx);
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}
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}
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if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
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delete state->mainPkt->req;
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delete state->mainPkt;
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}
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delete state;
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delete pkt->req;
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delete pkt;
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}
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template <class Impl>
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LSQUnit<Impl>::LSQUnit()
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: loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
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isStoreBlocked(false), isLoadBlocked(false),
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loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
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{
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}
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template<class Impl>
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void
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LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
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LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
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unsigned id)
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{
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cpu = cpu_ptr;
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iewStage = iew_ptr;
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DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
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switchedOut = false;
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cacheBlockMask = 0;
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lsq = lsq_ptr;
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lsqID = id;
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// Add 1 for the sentinel entry (they are circular queues).
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LQEntries = maxLQEntries + 1;
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SQEntries = maxSQEntries + 1;
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loadQueue.resize(LQEntries);
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storeQueue.resize(SQEntries);
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depCheckShift = params->LSQDepCheckShift;
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checkLoads = params->LSQCheckLoads;
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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cachePorts = params->cachePorts;
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retryPkt = NULL;
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memDepViolator = NULL;
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blockedLoadSeqNum = 0;
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needsTSO = params->needsTSO;
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}
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template<class Impl>
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std::string
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LSQUnit<Impl>::name() const
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{
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if (Impl::MaxThreads == 1) {
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return iewStage->name() + ".lsq";
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} else {
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return iewStage->name() + ".lsq.thread" + to_string(lsqID);
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::regStats()
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{
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lsqForwLoads
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.name(name() + ".forwLoads")
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.desc("Number of loads that had data forwarded from stores");
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invAddrLoads
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.name(name() + ".invAddrLoads")
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.desc("Number of loads ignored due to an invalid address");
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lsqSquashedLoads
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.name(name() + ".squashedLoads")
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.desc("Number of loads squashed");
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lsqIgnoredResponses
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.name(name() + ".ignoredResponses")
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.desc("Number of memory responses ignored because the instruction is squashed");
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lsqMemOrderViolation
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.name(name() + ".memOrderViolation")
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.desc("Number of memory ordering violations");
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lsqSquashedStores
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.name(name() + ".squashedStores")
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.desc("Number of stores squashed");
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invAddrSwpfs
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.name(name() + ".invAddrSwpfs")
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.desc("Number of software prefetches ignored due to an invalid address");
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lsqBlockedLoads
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.name(name() + ".blockedLoads")
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.desc("Number of blocked loads due to partial load-store forwarding");
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lsqRescheduledLoads
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.name(name() + ".rescheduledLoads")
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.desc("Number of loads that were rescheduled");
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lsqCacheBlocked
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.name(name() + ".cacheBlocked")
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.desc("Number of times an access to memory failed due to the cache being blocked");
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}
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template<class Impl>
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void
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LSQUnit<Impl>::setDcachePort(MasterPort *dcache_port)
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{
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dcachePort = dcache_port;
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearLQ()
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{
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loadQueue.clear();
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}
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template<class Impl>
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void
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LSQUnit<Impl>::clearSQ()
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{
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storeQueue.clear();
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}
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template<class Impl>
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void
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LSQUnit<Impl>::switchOut()
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{
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switchedOut = true;
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for (int i = 0; i < loadQueue.size(); ++i) {
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assert(!loadQueue[i]);
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loadQueue[i] = NULL;
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}
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assert(storesToWB == 0);
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}
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template<class Impl>
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void
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LSQUnit<Impl>::takeOverFrom()
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{
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switchedOut = false;
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loads = stores = storesToWB = 0;
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loadHead = loadTail = 0;
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storeHead = storeWBIdx = storeTail = 0;
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usedPorts = 0;
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memDepViolator = NULL;
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blockedLoadSeqNum = 0;
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stalled = false;
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isLoadBlocked = false;
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loadBlockedHandled = false;
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// Just incase the memory system changed out from under us
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cacheBlockMask = 0;
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}
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template<class Impl>
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void
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LSQUnit<Impl>::resizeLQ(unsigned size)
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{
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unsigned size_plus_sentinel = size + 1;
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assert(size_plus_sentinel >= LQEntries);
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if (size_plus_sentinel > LQEntries) {
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while (size_plus_sentinel > loadQueue.size()) {
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DynInstPtr dummy;
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loadQueue.push_back(dummy);
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LQEntries++;
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}
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} else {
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LQEntries = size_plus_sentinel;
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}
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}
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template<class Impl>
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void
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LSQUnit<Impl>::resizeSQ(unsigned size)
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{
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unsigned size_plus_sentinel = size + 1;
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if (size_plus_sentinel > SQEntries) {
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while (size_plus_sentinel > storeQueue.size()) {
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SQEntry dummy;
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storeQueue.push_back(dummy);
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SQEntries++;
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}
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} else {
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SQEntries = size_plus_sentinel;
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}
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insert(DynInstPtr &inst)
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{
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assert(inst->isMemRef());
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assert(inst->isLoad() || inst->isStore());
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if (inst->isLoad()) {
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insertLoad(inst);
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} else {
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insertStore(inst);
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}
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inst->setInLSQ();
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
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{
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assert((loadTail + 1) % LQEntries != loadHead);
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assert(loads < LQEntries);
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DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n",
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load_inst->pcState(), loadTail, load_inst->seqNum);
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load_inst->lqIdx = loadTail;
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if (stores == 0) {
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load_inst->sqIdx = -1;
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} else {
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load_inst->sqIdx = storeTail;
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}
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loadQueue[loadTail] = load_inst;
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incrLdIdx(loadTail);
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++loads;
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}
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template <class Impl>
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void
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LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
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{
|
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// Make sure it is not full before inserting an instruction.
|
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assert((storeTail + 1) % SQEntries != storeHead);
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assert(stores < SQEntries);
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DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n",
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store_inst->pcState(), storeTail, store_inst->seqNum);
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store_inst->sqIdx = storeTail;
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store_inst->lqIdx = loadTail;
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storeQueue[storeTail] = SQEntry(store_inst);
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incrStIdx(storeTail);
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++stores;
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}
|
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|
|
template <class Impl>
|
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typename Impl::DynInstPtr
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LSQUnit<Impl>::getMemDepViolator()
|
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{
|
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DynInstPtr temp = memDepViolator;
|
|
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memDepViolator = NULL;
|
|
|
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return temp;
|
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}
|
|
|
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template <class Impl>
|
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unsigned
|
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LSQUnit<Impl>::numFreeEntries()
|
|
{
|
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unsigned free_lq_entries = LQEntries - loads;
|
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unsigned free_sq_entries = SQEntries - stores;
|
|
|
|
// Both the LQ and SQ entries have an extra dummy entry to differentiate
|
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// empty/full conditions. Subtract 1 from the free entries.
|
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if (free_lq_entries < free_sq_entries) {
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return free_lq_entries - 1;
|
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} else {
|
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return free_sq_entries - 1;
|
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}
|
|
}
|
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|
|
template <class Impl>
|
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int
|
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LSQUnit<Impl>::numLoadsReady()
|
|
{
|
|
int load_idx = loadHead;
|
|
int retval = 0;
|
|
|
|
while (load_idx != loadTail) {
|
|
assert(loadQueue[load_idx]);
|
|
|
|
if (loadQueue[load_idx]->readyToIssue()) {
|
|
++retval;
|
|
}
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::checkSnoop(PacketPtr pkt)
|
|
{
|
|
int load_idx = loadHead;
|
|
|
|
if (!cacheBlockMask) {
|
|
assert(dcachePort);
|
|
Addr bs = dcachePort->peerBlockSize();
|
|
|
|
// Make sure we actually got a size
|
|
assert(bs != 0);
|
|
|
|
cacheBlockMask = ~(bs - 1);
|
|
}
|
|
|
|
// If this is the only load in the LSQ we don't care
|
|
if (load_idx == loadTail)
|
|
return;
|
|
incrLdIdx(load_idx);
|
|
|
|
DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr());
|
|
Addr invalidate_addr = pkt->getAddr() & cacheBlockMask;
|
|
while (load_idx != loadTail) {
|
|
DynInstPtr ld_inst = loadQueue[load_idx];
|
|
|
|
if (!ld_inst->effAddrValid || ld_inst->uncacheable()) {
|
|
incrLdIdx(load_idx);
|
|
continue;
|
|
}
|
|
|
|
Addr load_addr = ld_inst->physEffAddr & cacheBlockMask;
|
|
DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n",
|
|
ld_inst->seqNum, load_addr, invalidate_addr);
|
|
|
|
if (load_addr == invalidate_addr) {
|
|
if (ld_inst->possibleLoadViolation) {
|
|
DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n",
|
|
ld_inst->physEffAddr, pkt->getAddr(), ld_inst->seqNum);
|
|
|
|
// Mark the load for re-execution
|
|
ld_inst->fault = new ReExec;
|
|
} else {
|
|
// If a older load checks this and it's true
|
|
// then we might have missed the snoop
|
|
// in which case we need to invalidate to be sure
|
|
ld_inst->hitExternalSnoop = true;
|
|
}
|
|
}
|
|
incrLdIdx(load_idx);
|
|
}
|
|
return;
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
LSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst)
|
|
{
|
|
Addr inst_eff_addr1 = inst->effAddr >> depCheckShift;
|
|
Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift;
|
|
|
|
/** @todo in theory you only need to check an instruction that has executed
|
|
* however, there isn't a good way in the pipeline at the moment to check
|
|
* all instructions that will execute before the store writes back. Thus,
|
|
* like the implementation that came before it, we're overly conservative.
|
|
*/
|
|
while (load_idx != loadTail) {
|
|
DynInstPtr ld_inst = loadQueue[load_idx];
|
|
if (!ld_inst->effAddrValid || ld_inst->uncacheable()) {
|
|
incrLdIdx(load_idx);
|
|
continue;
|
|
}
|
|
|
|
Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift;
|
|
Addr ld_eff_addr2 =
|
|
(ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift;
|
|
|
|
if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) {
|
|
if (inst->isLoad()) {
|
|
// If this load is to the same block as an external snoop
|
|
// invalidate that we've observed then the load needs to be
|
|
// squashed as it could have newer data
|
|
if (ld_inst->hitExternalSnoop) {
|
|
if (!memDepViolator ||
|
|
ld_inst->seqNum < memDepViolator->seqNum) {
|
|
DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] "
|
|
"and [sn:%lli] at address %#x\n",
|
|
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
|
|
memDepViolator = ld_inst;
|
|
|
|
++lsqMemOrderViolation;
|
|
|
|
return new GenericISA::M5PanicFault(
|
|
"Detected fault with inst [sn:%lli] and "
|
|
"[sn:%lli] at address %#x\n",
|
|
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
|
|
}
|
|
}
|
|
|
|
// Otherwise, mark the load has a possible load violation
|
|
// and if we see a snoop before it's commited, we need to squash
|
|
ld_inst->possibleLoadViolation = true;
|
|
DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x"
|
|
" between instructions [sn:%lli] and [sn:%lli]\n",
|
|
inst_eff_addr1, inst->seqNum, ld_inst->seqNum);
|
|
} else {
|
|
// A load/store incorrectly passed this store.
|
|
// Check if we already have a violator, or if it's newer
|
|
// squash and refetch.
|
|
if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum)
|
|
break;
|
|
|
|
DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and "
|
|
"[sn:%lli] at address %#x\n",
|
|
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
|
|
memDepViolator = ld_inst;
|
|
|
|
++lsqMemOrderViolation;
|
|
|
|
return new GenericISA::M5PanicFault("Detected fault with "
|
|
"inst [sn:%lli] and [sn:%lli] at address %#x\n",
|
|
inst->seqNum, ld_inst->seqNum, ld_eff_addr1);
|
|
}
|
|
}
|
|
|
|
incrLdIdx(load_idx);
|
|
}
|
|
return NoFault;
|
|
}
|
|
|
|
|
|
|
|
|
|
template <class Impl>
|
|
Fault
|
|
LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
|
|
{
|
|
using namespace TheISA;
|
|
// Execute a specific load.
|
|
Fault load_fault = NoFault;
|
|
|
|
DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n",
|
|
inst->pcState(), inst->seqNum);
|
|
|
|
assert(!inst->isSquashed());
|
|
|
|
load_fault = inst->initiateAcc();
|
|
|
|
if (inst->isTranslationDelayed() &&
|
|
load_fault == NoFault)
|
|
return load_fault;
|
|
|
|
// If the instruction faulted or predicated false, then we need to send it
|
|
// along to commit without the instruction completing.
|
|
if (load_fault != NoFault || inst->readPredicate() == false) {
|
|
// Send this instruction to commit, also make sure iew stage
|
|
// realizes there is activity.
|
|
// Mark it as executed unless it is an uncached load that
|
|
// needs to hit the head of commit.
|
|
if (inst->readPredicate() == false)
|
|
inst->forwardOldRegs();
|
|
DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n",
|
|
inst->seqNum,
|
|
(load_fault != NoFault ? "fault" : "predication"));
|
|
if (!(inst->hasRequest() && inst->uncacheable()) ||
|
|
inst->isAtCommit()) {
|
|
inst->setExecuted();
|
|
}
|
|
iewStage->instToCommit(inst);
|
|
iewStage->activityThisCycle();
|
|
} else if (!loadBlocked()) {
|
|
assert(inst->effAddrValid);
|
|
int load_idx = inst->lqIdx;
|
|
incrLdIdx(load_idx);
|
|
|
|
if (checkLoads)
|
|
return checkViolations(load_idx, inst);
|
|
}
|
|
|
|
return load_fault;
|
|
}
|
|
|
|
template <class Impl>
|
|
Fault
|
|
LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
|
|
{
|
|
using namespace TheISA;
|
|
// Make sure that a store exists.
|
|
assert(stores != 0);
|
|
|
|
int store_idx = store_inst->sqIdx;
|
|
|
|
DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n",
|
|
store_inst->pcState(), store_inst->seqNum);
|
|
|
|
assert(!store_inst->isSquashed());
|
|
|
|
// Check the recently completed loads to see if any match this store's
|
|
// address. If so, then we have a memory ordering violation.
|
|
int load_idx = store_inst->lqIdx;
|
|
|
|
Fault store_fault = store_inst->initiateAcc();
|
|
|
|
if (store_inst->isTranslationDelayed() &&
|
|
store_fault == NoFault)
|
|
return store_fault;
|
|
|
|
if (store_inst->readPredicate() == false)
|
|
store_inst->forwardOldRegs();
|
|
|
|
if (storeQueue[store_idx].size == 0) {
|
|
DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n",
|
|
store_inst->pcState(), store_inst->seqNum);
|
|
|
|
return store_fault;
|
|
} else if (store_inst->readPredicate() == false) {
|
|
DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n",
|
|
store_inst->seqNum);
|
|
return store_fault;
|
|
}
|
|
|
|
assert(store_fault == NoFault);
|
|
|
|
if (store_inst->isStoreConditional()) {
|
|
// Store conditionals need to set themselves as able to
|
|
// writeback if we haven't had a fault by here.
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
++storesToWB;
|
|
}
|
|
|
|
return checkViolations(load_idx, store_inst);
|
|
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoad()
|
|
{
|
|
assert(loadQueue[loadHead]);
|
|
|
|
DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n",
|
|
loadQueue[loadHead]->pcState());
|
|
|
|
loadQueue[loadHead] = NULL;
|
|
|
|
incrLdIdx(loadHead);
|
|
|
|
--loads;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
|
|
{
|
|
assert(loads == 0 || loadQueue[loadHead]);
|
|
|
|
while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
|
|
commitLoad();
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
|
|
{
|
|
assert(stores == 0 || storeQueue[storeHead].inst);
|
|
|
|
int store_idx = storeHead;
|
|
|
|
while (store_idx != storeTail) {
|
|
assert(storeQueue[store_idx].inst);
|
|
// Mark any stores that are now committed and have not yet
|
|
// been marked as able to write back.
|
|
if (!storeQueue[store_idx].canWB) {
|
|
if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
|
|
break;
|
|
}
|
|
DPRINTF(LSQUnit, "Marking store as able to write back, PC "
|
|
"%s [sn:%lli]\n",
|
|
storeQueue[store_idx].inst->pcState(),
|
|
storeQueue[store_idx].inst->seqNum);
|
|
|
|
storeQueue[store_idx].canWB = true;
|
|
|
|
++storesToWB;
|
|
}
|
|
|
|
incrStIdx(store_idx);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::writebackPendingStore()
|
|
{
|
|
if (hasPendingPkt) {
|
|
assert(pendingPkt != NULL);
|
|
|
|
// If the cache is blocked, this will store the packet for retry.
|
|
if (sendStore(pendingPkt)) {
|
|
storePostSend(pendingPkt);
|
|
}
|
|
pendingPkt = NULL;
|
|
hasPendingPkt = false;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::writebackStores()
|
|
{
|
|
// First writeback the second packet from any split store that didn't
|
|
// complete last cycle because there weren't enough cache ports available.
|
|
if (TheISA::HasUnalignedMemAcc) {
|
|
writebackPendingStore();
|
|
}
|
|
|
|
while (storesToWB > 0 &&
|
|
storeWBIdx != storeTail &&
|
|
storeQueue[storeWBIdx].inst &&
|
|
storeQueue[storeWBIdx].canWB &&
|
|
((!needsTSO) || (!storeInFlight)) &&
|
|
usedPorts < cachePorts) {
|
|
|
|
if (isStoreBlocked || lsq->cacheBlocked()) {
|
|
DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
|
|
" is blocked!\n");
|
|
break;
|
|
}
|
|
|
|
// Store didn't write any data so no need to write it back to
|
|
// memory.
|
|
if (storeQueue[storeWBIdx].size == 0) {
|
|
completeStore(storeWBIdx);
|
|
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
|
}
|
|
|
|
++usedPorts;
|
|
|
|
if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
|
|
incrStIdx(storeWBIdx);
|
|
|
|
continue;
|
|
}
|
|
|
|
assert(storeQueue[storeWBIdx].req);
|
|
assert(!storeQueue[storeWBIdx].committed);
|
|
|
|
if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) {
|
|
assert(storeQueue[storeWBIdx].sreqLow);
|
|
assert(storeQueue[storeWBIdx].sreqHigh);
|
|
}
|
|
|
|
DynInstPtr inst = storeQueue[storeWBIdx].inst;
|
|
|
|
Request *req = storeQueue[storeWBIdx].req;
|
|
RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
|
|
RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
|
|
|
|
storeQueue[storeWBIdx].committed = true;
|
|
|
|
assert(!inst->memData);
|
|
inst->memData = new uint8_t[64];
|
|
|
|
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
|
|
|
|
MemCmd command =
|
|
req->isSwap() ? MemCmd::SwapReq :
|
|
(req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
|
|
PacketPtr data_pkt;
|
|
PacketPtr snd_data_pkt = NULL;
|
|
|
|
LSQSenderState *state = new LSQSenderState;
|
|
state->isLoad = false;
|
|
state->idx = storeWBIdx;
|
|
state->inst = inst;
|
|
|
|
if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) {
|
|
|
|
// Build a single data packet if the store isn't split.
|
|
data_pkt = new Packet(req, command);
|
|
data_pkt->dataStatic(inst->memData);
|
|
data_pkt->senderState = state;
|
|
} else {
|
|
// Create two packets if the store is split in two.
|
|
data_pkt = new Packet(sreqLow, command);
|
|
snd_data_pkt = new Packet(sreqHigh, command);
|
|
|
|
data_pkt->dataStatic(inst->memData);
|
|
snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize());
|
|
|
|
data_pkt->senderState = state;
|
|
snd_data_pkt->senderState = state;
|
|
|
|
state->isSplit = true;
|
|
state->outstanding = 2;
|
|
|
|
// Can delete the main request now.
|
|
delete req;
|
|
req = sreqLow;
|
|
}
|
|
|
|
DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s "
|
|
"to Addr:%#x, data:%#x [sn:%lli]\n",
|
|
storeWBIdx, inst->pcState(),
|
|
req->getPaddr(), (int)*(inst->memData),
|
|
inst->seqNum);
|
|
|
|
// @todo: Remove this SC hack once the memory system handles it.
|
|
if (inst->isStoreConditional()) {
|
|
assert(!storeQueue[storeWBIdx].isSplit);
|
|
// Disable recording the result temporarily. Writing to
|
|
// misc regs normally updates the result, but this is not
|
|
// the desired behavior when handling store conditionals.
|
|
inst->recordResult = false;
|
|
bool success = TheISA::handleLockedWrite(inst.get(), req);
|
|
inst->recordResult = true;
|
|
|
|
if (!success) {
|
|
// Instantly complete this store.
|
|
DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. "
|
|
"Instantly completing it.\n",
|
|
inst->seqNum);
|
|
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
|
|
cpu->schedule(wb, curTick() + 1);
|
|
if (cpu->checker) {
|
|
// Make sure to set the LLSC data for verification
|
|
// if checker is loaded
|
|
inst->reqToVerify->setExtraData(0);
|
|
inst->completeAcc(data_pkt);
|
|
}
|
|
completeStore(storeWBIdx);
|
|
incrStIdx(storeWBIdx);
|
|
continue;
|
|
}
|
|
} else {
|
|
// Non-store conditionals do not need a writeback.
|
|
state->noWB = true;
|
|
}
|
|
|
|
bool split =
|
|
TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit;
|
|
|
|
ThreadContext *thread = cpu->tcBase(lsqID);
|
|
|
|
if (req->isMmappedIpr()) {
|
|
assert(!inst->isStoreConditional());
|
|
TheISA::handleIprWrite(thread, data_pkt);
|
|
delete data_pkt;
|
|
if (split) {
|
|
assert(snd_data_pkt->req->isMmappedIpr());
|
|
TheISA::handleIprWrite(thread, snd_data_pkt);
|
|
delete snd_data_pkt;
|
|
delete sreqLow;
|
|
delete sreqHigh;
|
|
}
|
|
delete state;
|
|
delete req;
|
|
completeStore(storeWBIdx);
|
|
incrStIdx(storeWBIdx);
|
|
} else if (!sendStore(data_pkt)) {
|
|
DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
|
|
"retry later\n",
|
|
inst->seqNum);
|
|
|
|
// Need to store the second packet, if split.
|
|
if (split) {
|
|
state->pktToSend = true;
|
|
state->pendingPacket = snd_data_pkt;
|
|
}
|
|
} else {
|
|
|
|
// If split, try to send the second packet too
|
|
if (split) {
|
|
assert(snd_data_pkt);
|
|
|
|
// Ensure there are enough ports to use.
|
|
if (usedPorts < cachePorts) {
|
|
++usedPorts;
|
|
if (sendStore(snd_data_pkt)) {
|
|
storePostSend(snd_data_pkt);
|
|
} else {
|
|
DPRINTF(IEW, "D-Cache became blocked when writing"
|
|
" [sn:%lli] second packet, will retry later\n",
|
|
inst->seqNum);
|
|
}
|
|
} else {
|
|
|
|
// Store the packet for when there's free ports.
|
|
assert(pendingPkt == NULL);
|
|
pendingPkt = snd_data_pkt;
|
|
hasPendingPkt = true;
|
|
}
|
|
} else {
|
|
|
|
// Not a split store.
|
|
storePostSend(data_pkt);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Not sure this should set it to 0.
|
|
usedPorts = 0;
|
|
|
|
assert(stores >= 0 && storesToWB >= 0);
|
|
}
|
|
|
|
/*template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
|
|
{
|
|
list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
|
|
mshrSeqNums.end(),
|
|
seqNum);
|
|
|
|
if (mshr_it != mshrSeqNums.end()) {
|
|
mshrSeqNums.erase(mshr_it);
|
|
DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
|
|
}
|
|
}*/
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
|
|
{
|
|
DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
|
|
"(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
|
|
|
|
int load_idx = loadTail;
|
|
decrLdIdx(load_idx);
|
|
|
|
while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
|
|
DPRINTF(LSQUnit,"Load Instruction PC %s squashed, "
|
|
"[sn:%lli]\n",
|
|
loadQueue[load_idx]->pcState(),
|
|
loadQueue[load_idx]->seqNum);
|
|
|
|
if (isStalled() && load_idx == stallingLoadIdx) {
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
stallingLoadIdx = 0;
|
|
}
|
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
loadQueue[load_idx]->setSquashed();
|
|
loadQueue[load_idx] = NULL;
|
|
--loads;
|
|
|
|
// Inefficient!
|
|
loadTail = load_idx;
|
|
|
|
decrLdIdx(load_idx);
|
|
++lsqSquashedLoads;
|
|
}
|
|
|
|
if (isLoadBlocked) {
|
|
if (squashed_num < blockedLoadSeqNum) {
|
|
isLoadBlocked = false;
|
|
loadBlockedHandled = false;
|
|
blockedLoadSeqNum = 0;
|
|
}
|
|
}
|
|
|
|
if (memDepViolator && squashed_num < memDepViolator->seqNum) {
|
|
memDepViolator = NULL;
|
|
}
|
|
|
|
int store_idx = storeTail;
|
|
decrStIdx(store_idx);
|
|
|
|
while (stores != 0 &&
|
|
storeQueue[store_idx].inst->seqNum > squashed_num) {
|
|
// Instructions marked as can WB are already committed.
|
|
if (storeQueue[store_idx].canWB) {
|
|
break;
|
|
}
|
|
|
|
DPRINTF(LSQUnit,"Store Instruction PC %s squashed, "
|
|
"idx:%i [sn:%lli]\n",
|
|
storeQueue[store_idx].inst->pcState(),
|
|
store_idx, storeQueue[store_idx].inst->seqNum);
|
|
|
|
// I don't think this can happen. It should have been cleared
|
|
// by the stalling load.
|
|
if (isStalled() &&
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
panic("Is stalled should have been cleared by stalling load!\n");
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
}
|
|
|
|
// Clear the smart pointer to make sure it is decremented.
|
|
storeQueue[store_idx].inst->setSquashed();
|
|
storeQueue[store_idx].inst = NULL;
|
|
storeQueue[store_idx].canWB = 0;
|
|
|
|
// Must delete request now that it wasn't handed off to
|
|
// memory. This is quite ugly. @todo: Figure out the proper
|
|
// place to really handle request deletes.
|
|
delete storeQueue[store_idx].req;
|
|
if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
|
|
delete storeQueue[store_idx].sreqLow;
|
|
delete storeQueue[store_idx].sreqHigh;
|
|
|
|
storeQueue[store_idx].sreqLow = NULL;
|
|
storeQueue[store_idx].sreqHigh = NULL;
|
|
}
|
|
|
|
storeQueue[store_idx].req = NULL;
|
|
--stores;
|
|
|
|
// Inefficient!
|
|
storeTail = store_idx;
|
|
|
|
decrStIdx(store_idx);
|
|
++lsqSquashedStores;
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::storePostSend(PacketPtr pkt)
|
|
{
|
|
if (isStalled() &&
|
|
storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
"load idx:%i\n",
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
}
|
|
|
|
if (!storeQueue[storeWBIdx].inst->isStoreConditional()) {
|
|
// The store is basically completed at this time. This
|
|
// only works so long as the checker doesn't try to
|
|
// verify the value in memory for stores.
|
|
storeQueue[storeWBIdx].inst->setCompleted();
|
|
|
|
if (cpu->checker) {
|
|
cpu->checker->verify(storeQueue[storeWBIdx].inst);
|
|
}
|
|
}
|
|
|
|
if (needsTSO) {
|
|
storeInFlight = true;
|
|
}
|
|
|
|
incrStIdx(storeWBIdx);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
|
|
{
|
|
iewStage->wakeCPU();
|
|
|
|
// Squashed instructions do not need to complete their access.
|
|
if (inst->isSquashed()) {
|
|
iewStage->decrWb(inst->seqNum);
|
|
assert(!inst->isStore());
|
|
++lsqIgnoredResponses;
|
|
return;
|
|
}
|
|
|
|
if (!inst->isExecuted()) {
|
|
inst->setExecuted();
|
|
|
|
// Complete access to copy data to proper place.
|
|
inst->completeAcc(pkt);
|
|
}
|
|
|
|
// Need to insert instruction into queue to commit
|
|
iewStage->instToCommit(inst);
|
|
|
|
iewStage->activityThisCycle();
|
|
|
|
// see if this load changed the PC
|
|
iewStage->checkMisprediction(inst);
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::completeStore(int store_idx)
|
|
{
|
|
assert(storeQueue[store_idx].inst);
|
|
storeQueue[store_idx].completed = true;
|
|
--storesToWB;
|
|
// A bit conservative because a store completion may not free up entries,
|
|
// but hopefully avoids two store completions in one cycle from making
|
|
// the CPU tick twice.
|
|
cpu->wakeCPU();
|
|
cpu->activityThisCycle();
|
|
|
|
if (store_idx == storeHead) {
|
|
do {
|
|
incrStIdx(storeHead);
|
|
|
|
--stores;
|
|
} while (storeQueue[storeHead].completed &&
|
|
storeHead != storeTail);
|
|
|
|
iewStage->updateLSQNextCycle = true;
|
|
}
|
|
|
|
DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
|
|
"idx:%i\n",
|
|
storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
|
|
|
|
if (isStalled() &&
|
|
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
|
|
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
|
|
"load idx:%i\n",
|
|
stallingStoreIsn, stallingLoadIdx);
|
|
stalled = false;
|
|
stallingStoreIsn = 0;
|
|
iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
|
|
}
|
|
|
|
storeQueue[store_idx].inst->setCompleted();
|
|
|
|
if (needsTSO) {
|
|
storeInFlight = false;
|
|
}
|
|
|
|
// Tell the checker we've completed this instruction. Some stores
|
|
// may get reported twice to the checker, but the checker can
|
|
// handle that case.
|
|
if (cpu->checker) {
|
|
cpu->checker->verify(storeQueue[store_idx].inst);
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
bool
|
|
LSQUnit<Impl>::sendStore(PacketPtr data_pkt)
|
|
{
|
|
if (!dcachePort->sendTimingReq(data_pkt)) {
|
|
// Need to handle becoming blocked on a store.
|
|
isStoreBlocked = true;
|
|
++lsqCacheBlocked;
|
|
assert(retryPkt == NULL);
|
|
retryPkt = data_pkt;
|
|
lsq->setRetryTid(lsqID);
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::recvRetry()
|
|
{
|
|
if (isStoreBlocked) {
|
|
DPRINTF(LSQUnit, "Receiving retry: store blocked\n");
|
|
assert(retryPkt != NULL);
|
|
|
|
LSQSenderState *state =
|
|
dynamic_cast<LSQSenderState *>(retryPkt->senderState);
|
|
|
|
if (dcachePort->sendTimingReq(retryPkt)) {
|
|
// Don't finish the store unless this is the last packet.
|
|
if (!TheISA::HasUnalignedMemAcc || !state->pktToSend ||
|
|
state->pendingPacket == retryPkt) {
|
|
state->pktToSend = false;
|
|
storePostSend(retryPkt);
|
|
}
|
|
retryPkt = NULL;
|
|
isStoreBlocked = false;
|
|
lsq->setRetryTid(InvalidThreadID);
|
|
|
|
// Send any outstanding packet.
|
|
if (TheISA::HasUnalignedMemAcc && state->pktToSend) {
|
|
assert(state->pendingPacket);
|
|
if (sendStore(state->pendingPacket)) {
|
|
storePostSend(state->pendingPacket);
|
|
}
|
|
}
|
|
} else {
|
|
// Still blocked!
|
|
++lsqCacheBlocked;
|
|
lsq->setRetryTid(lsqID);
|
|
}
|
|
} else if (isLoadBlocked) {
|
|
DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
|
|
"no need to resend packet.\n");
|
|
} else {
|
|
DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n");
|
|
}
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::incrStIdx(int &store_idx)
|
|
{
|
|
if (++store_idx >= SQEntries)
|
|
store_idx = 0;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::decrStIdx(int &store_idx)
|
|
{
|
|
if (--store_idx < 0)
|
|
store_idx += SQEntries;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::incrLdIdx(int &load_idx)
|
|
{
|
|
if (++load_idx >= LQEntries)
|
|
load_idx = 0;
|
|
}
|
|
|
|
template <class Impl>
|
|
inline void
|
|
LSQUnit<Impl>::decrLdIdx(int &load_idx)
|
|
{
|
|
if (--load_idx < 0)
|
|
load_idx += LQEntries;
|
|
}
|
|
|
|
template <class Impl>
|
|
void
|
|
LSQUnit<Impl>::dumpInsts()
|
|
{
|
|
cprintf("Load store queue: Dumping instructions.\n");
|
|
cprintf("Load queue size: %i\n", loads);
|
|
cprintf("Load queue: ");
|
|
|
|
int load_idx = loadHead;
|
|
|
|
while (load_idx != loadTail && loadQueue[load_idx]) {
|
|
cprintf("%s ", loadQueue[load_idx]->pcState());
|
|
|
|
incrLdIdx(load_idx);
|
|
}
|
|
|
|
cprintf("Store queue size: %i\n", stores);
|
|
cprintf("Store queue: ");
|
|
|
|
int store_idx = storeHead;
|
|
|
|
while (store_idx != storeTail && storeQueue[store_idx].inst) {
|
|
cprintf("%s ", storeQueue[store_idx].inst->pcState());
|
|
|
|
incrStIdx(store_idx);
|
|
}
|
|
|
|
cprintf("\n");
|
|
}
|