499 lines
55 KiB
Plaintext
499 lines
55 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000012 # Number of seconds simulated
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sim_ticks 12002500 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 25819 # Simulator instruction rate (inst/s)
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host_tick_rate 48521023 # Simulator tick rate (ticks/s)
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host_mem_usage 243716 # Number of bytes of host memory used
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host_seconds 0.25 # Real time elapsed on the host
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sim_insts 6386 # Number of instructions simulated
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 1863 # DTB read hits
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system.cpu.dtb.read_misses 45 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 1908 # DTB read accesses
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system.cpu.dtb.write_hits 1047 # DTB write hits
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system.cpu.dtb.write_misses 28 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 1075 # DTB write accesses
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system.cpu.dtb.data_hits 2910 # DTB hits
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system.cpu.dtb.data_misses 73 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 2983 # DTB accesses
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system.cpu.itb.fetch_hits 2044 # ITB hits
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system.cpu.itb.fetch_misses 29 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 2073 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 24006 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 2516 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 1462 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 458 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 1947 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 723 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 372 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 7155 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 14481 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 2516 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 1095 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 2626 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 1554 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 1112 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 631 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 2044 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 12602 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 1.149103 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 2.531397 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 9976 79.16% 79.16% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 274 2.17% 81.34% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 231 1.83% 83.17% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 220 1.75% 84.92% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 235 1.86% 86.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 176 1.40% 88.18% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 257 2.04% 90.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 141 1.12% 91.33% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 1092 8.67% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 12602 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.104807 # Number of branch fetches per cycle
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system.cpu.fetch.rate 0.603224 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 7976 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 1126 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 2455 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 976 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 216 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 85 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 13403 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 976 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 8164 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 432 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 358 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 2326 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 346 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 12866 # Number of instructions processed by rename
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system.cpu.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 291 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 9599 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 16086 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 16069 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 5016 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 28 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 881 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 2397 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 1265 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 11578 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 9768 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 4900 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 2850 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 12602 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 0.775115 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 1.397410 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 8516 67.58% 67.58% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 1470 11.66% 79.24% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 1066 8.46% 87.70% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 684 5.43% 93.13% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 441 3.50% 96.63% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 254 2.02% 98.64% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 129 1.02% 99.67% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 30 0.24% 99.90% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 12602 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 13 12.38% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 12.38% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 54 51.43% 63.81% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 38 36.19% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 6583 67.39% 67.41% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.42% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.42% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.44% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 2078 21.27% 88.72% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 1102 11.28% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 9768 # Type of FU issued
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system.cpu.iq.rate 0.406898 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 105 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.010749 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 32267 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 16511 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 8987 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 9860 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses
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system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores
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system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
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system.cpu.iew.lsq.thread0.squashedLoads 1212 # Number of loads squashed
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system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
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system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations
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system.cpu.iew.lsq.thread0.squashedStores 400 # Number of stores squashed
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system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
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system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
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system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
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system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
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system.cpu.iew.iewSquashCycles 976 # Number of cycles IEW is squashing
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system.cpu.iew.iewBlockCycles 150 # Number of cycles IEW is blocking
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system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking
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system.cpu.iew.iewDispatchedInsts 11685 # Number of instructions dispatched to IQ
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system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch
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system.cpu.iew.iewDispLoadInsts 2397 # Number of dispatched load instructions
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system.cpu.iew.iewDispStoreInsts 1265 # Number of dispatched store instructions
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system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions
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system.cpu.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall
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system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
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system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations
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system.cpu.iew.predictedTakenIncorrect 118 # Number of branches that were predicted taken incorrectly
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system.cpu.iew.predictedNotTakenIncorrect 327 # Number of branches that were predicted not taken incorrectly
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system.cpu.iew.branchMispredicts 445 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecutedInsts 9324 # Number of executed instructions
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system.cpu.iew.iewExecLoadInsts 1918 # Number of load instructions executed
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system.cpu.iew.iewExecSquashedInsts 444 # Number of squashed instructions skipped in execute
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system.cpu.iew.exec_swp 0 # number of swp insts executed
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system.cpu.iew.exec_nop 80 # number of nop insts executed
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system.cpu.iew.exec_refs 2995 # number of memory reference insts executed
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system.cpu.iew.exec_branches 1503 # Number of branches executed
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system.cpu.iew.exec_stores 1077 # Number of stores executed
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system.cpu.iew.exec_rate 0.388403 # Inst execution rate
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|
system.cpu.iew.wb_sent 9127 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 8997 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 4717 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 6401 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 0.374781 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.736916 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 5279 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 11626 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 0.550748 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 1.411308 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 8945 76.94% 76.94% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 1414 12.16% 89.10% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 463 3.98% 93.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 244 2.10% 95.18% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 156 1.34% 96.53% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 87 0.75% 97.27% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 110 0.95% 98.22% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 44 0.38% 98.60% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 163 1.40% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 11626 # Number of insts commited each cycle
|
|
system.cpu.commit.count 6403 # Number of instructions committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 2050 # Number of memory references committed
|
|
system.cpu.commit.loads 1185 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 1051 # Number of branches committed
|
|
system.cpu.commit.fp_insts 10 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 6321 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 127 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 163 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 22794 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 24351 # The number of ROB writes
|
|
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 11404 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 6386 # Number of Instructions Simulated
|
|
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
|
|
system.cpu.cpi 3.759161 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 3.759161 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.266017 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 0.266017 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 11850 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 6735 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 8 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 2 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 1 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 0 # number of replacements
|
|
system.cpu.icache.tagsinuse 159.654959 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 1612 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 311 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 5.183280 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::0 159.654959 # Average occupied blocks per context
|
|
system.cpu.icache.occ_percent::0 0.077957 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits 1612 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits 1612 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits 1612 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses 432 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses 432 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses 432 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency 15402000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency 15402000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency 15402000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses 2044 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses 2044 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses 2044 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate 0.211350 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate 0.211350 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate 0.211350 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency 35652.777778 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency 35652.777778 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency 35652.777778 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.writebacks 0 # number of writebacks
|
|
system.cpu.icache.ReadReq_mshr_hits 121 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits 121 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits 121 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses 311 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses 311 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses 311 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency 10985500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency 10985500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency 10985500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate 0.152153 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate 0.152153 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate 0.152153 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.151125 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency 35323.151125 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 0 # number of replacements
|
|
system.cpu.dcache.tagsinuse 109.289403 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 2155 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 12.385057 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::0 109.289403 # Average occupied blocks per context
|
|
system.cpu.dcache.occ_percent::0 0.026682 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits 1646 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits 509 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits 2155 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits 2155 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses 155 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses 356 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses 511 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses 511 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency 5502500 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency 12467500 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency 17970000 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency 17970000 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses 1801 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses 2666 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses 2666 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate 0.086063 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate 0.411561 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate 0.191673 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate 0.191673 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency 35500 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency 35166.340509 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency 35166.340509 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks 0 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits 283 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits 337 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits 337 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses 101 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses 174 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses 174 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency 3654000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency 2611500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency 6265500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency 6265500 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate 0.056080 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate 0.065266 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate 0.065266 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36178.217822 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency 36008.620690 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 221.186144 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 411 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.002433 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::0 221.186144 # Average occupied blocks per context
|
|
system.cpu.l2cache.occ_percent::0 0.006750 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits 1 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses 411 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses 484 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses 484 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency 14128000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency 2513500 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency 16641500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency 16641500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses 412 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses 485 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses 485 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate 0.997573 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate 0.997938 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate 0.997938 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency 34374.695864 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency 34383.264463 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency 34383.264463 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks 0 # number of writebacks
|
|
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses 411 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses 484 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses 484 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency 12819000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency 15105000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency 15105000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997573 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate 0.997938 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate 0.997938 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.781022 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.677686 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
|
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|