2f30950143
We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother.
982 lines
31 KiB
Plaintext
982 lines
31 KiB
Plaintext
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/*
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* Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id$
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*
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*/
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machine(L1Cache, "Directory protocol") {
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MessageBuffer requestFromCache, network="To", virtual_network="0", ordered="false";
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MessageBuffer responseFromCache, network="To", virtual_network="2", ordered="false";
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MessageBuffer unblockFromCache, network="To", virtual_network="3", ordered="false";
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MessageBuffer forwardToCache, network="From", virtual_network="1", ordered="false";
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MessageBuffer responseToCache, network="From", virtual_network="2", ordered="false";
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// STATES
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enumeration(State, desc="Cache states", default="L1Cache_State_I") {
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// Base states
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NP, desc="Not Present";
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I, desc="Idle";
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S, desc="Shared";
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O, desc="Owned";
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E, desc="Exclusive (clean)";
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M, desc="Modified (dirty)";
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MM, desc="Modified (dirty and locally modified)";
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// Transient States
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IM, "IM", desc="Issued GetX";
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SM, "SM", desc="Issued GetX, we still have an old copy of the line";
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OM, "OM", desc="Issued GetX, received data";
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IS, "IS", desc="Issued GetS";
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OI, "OI", desc="Issued PutO, waiting for ack";
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MI, "MI", desc="Issued PutX, waiting for ack";
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II, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
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}
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// EVENTS
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enumeration(Event, desc="Cache events") {
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Load, desc="Load request from the processor";
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Ifetch, desc="I-fetch request from the processor";
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Store, desc="Store request from the processor";
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L2_Replacement, desc="Replacement";
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L1_to_L2, desc="L1 to L2 transfer";
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L2_to_L1D, desc="L2 to L1-Data transfer";
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L2_to_L1I, desc="L2 to L1-Instruction transfer";
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// Requests
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Own_GETX, desc="We observe our own GetX forwarded back to us";
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Fwd_GETX, desc="A GetX from another processor";
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Fwd_GETS, desc="A GetS from another processor";
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Inv, desc="Invalidations from the directory";
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// Responses
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Ack, desc="Received an ack message";
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Data, desc="Received a data message, responder has a shared copy";
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Exclusive_Data_Clean, desc="Received a data message, no other processor has it, data is clean";
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Exclusive_Data_Dirty, desc="Received a data message, no other processor has it, data is dirty";
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Writeback_Ack, desc="Writeback O.K. from directory";
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Writeback_Nack, desc="Writeback not O.K. from directory";
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// Triggers
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All_acks, desc="Received all required data and message acks";
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}
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// TYPES
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// CacheEntry
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structure(Entry, desc="...", interface="AbstractCacheEntry") {
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State CacheState, desc="cache state";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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DataBlock DataBlk, desc="data for the block";
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}
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// TBE fields
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structure(TBE, desc="...") {
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State TBEState, desc="Transient state";
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DataBlock DataBlk, desc="data for the block, required for concurrent writebacks";
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bool Dirty, desc="Is the data dirty (different than memory)?";
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int NumPendingMsgs, default="0", desc="Number of acks/data messages that this processor is waiting for";
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}
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external_type(CacheMemory) {
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bool cacheAvail(Address);
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Address cacheProbe(Address);
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void allocate(Address);
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void deallocate(Address);
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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}
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external_type(TBETable) {
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TBE lookup(Address);
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void allocate(Address);
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void deallocate(Address);
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bool isPresent(Address);
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}
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MessageBuffer mandatoryQueue, abstract_chip_ptr="true", ordered="false";
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Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
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StoreBuffer storeBuffer, abstract_chip_ptr="true", constructor_hack="i";
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TBETable TBEs, template_hack="<L1Cache_TBE>";
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CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
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CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
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CacheMemory L2cacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L2_CACHE_NUM_SETS_BITS,L2_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L2"', abstract_chip_ptr="true";
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Entry getCacheEntry(Address addr), return_by_ref="yes" {
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if (L2cacheMemory.isTagPresent(addr)) {
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return L2cacheMemory[addr];
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} else if (L1DcacheMemory.isTagPresent(addr)) {
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return L1DcacheMemory[addr];
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} else {
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return L1IcacheMemory[addr];
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}
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}
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void changePermission(Address addr, AccessPermission permission) {
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if (L2cacheMemory.isTagPresent(addr)) {
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return L2cacheMemory.changePermission(addr, permission);
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} else if (L1DcacheMemory.isTagPresent(addr)) {
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return L1DcacheMemory.changePermission(addr, permission);
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} else {
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return L1IcacheMemory.changePermission(addr, permission);
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}
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}
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bool isCacheTagPresent(Address addr) {
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return (L2cacheMemory.isTagPresent(addr) || L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
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}
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State getState(Address addr) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
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assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
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if(TBEs.isPresent(addr)) {
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return TBEs[addr].TBEState;
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} else if (isCacheTagPresent(addr)) {
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return getCacheEntry(addr).CacheState;
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}
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return State:NP;
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}
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void setState(Address addr, State state) {
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assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
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assert((L1IcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
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assert((L1DcacheMemory.isTagPresent(addr) && L2cacheMemory.isTagPresent(addr)) == false);
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if (TBEs.isPresent(addr)) {
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TBEs[addr].TBEState := state;
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}
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if (isCacheTagPresent(addr)) {
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getCacheEntry(addr).CacheState := state;
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if (state == State:E) {
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assert(getCacheEntry(addr).Dirty == false);
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}
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if ((state == State:M) || (state == State:MM)) {
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assert(getCacheEntry(addr).Dirty == true);
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}
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// Set permission
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if (state == State:MM) {
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changePermission(addr, AccessPermission:Read_Write);
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} else if ((state == State:S) ||
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(state == State:O) ||
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(state == State:M) ||
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(state == State:E) ||
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(state == State:SM) ||
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(state == State:OM)) {
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changePermission(addr, AccessPermission:Read_Only);
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} else {
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changePermission(addr, AccessPermission:Invalid);
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}
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}
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}
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Event mandatory_request_type_to_event(CacheRequestType type) {
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if (type == CacheRequestType:LD) {
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return Event:Load;
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} else if (type == CacheRequestType:IFETCH) {
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return Event:Ifetch;
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} else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
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return Event:Store;
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} else {
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error("Invalid CacheRequestType");
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}
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}
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MessageBuffer triggerQueue, ordered="true";
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// ** OUT_PORTS **
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out_port(requestNetwork_out, RequestMsg, requestFromCache);
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out_port(responseNetwork_out, ResponseMsg, responseFromCache);
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out_port(unblockNetwork_out, ResponseMsg, unblockFromCache);
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out_port(triggerQueue_out, TriggerMsg, triggerQueue);
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// ** IN_PORTS **
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// Trigger Queue
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in_port(triggerQueue_in, TriggerMsg, triggerQueue) {
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if (triggerQueue_in.isReady()) {
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peek(triggerQueue_in, TriggerMsg) {
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if (in_msg.Type == TriggerType:ALL_ACKS) {
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trigger(Event:All_acks, in_msg.Address);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Nothing from the request network
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// Forward Network
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in_port(forwardToCache_in, RequestMsg, forwardToCache) {
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if (forwardToCache_in.isReady()) {
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peek(forwardToCache_in, RequestMsg) {
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if (in_msg.Type == CoherenceRequestType:GETX) {
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if (in_msg.Requestor == machineID) {
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trigger(Event:Own_GETX, in_msg.Address);
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} else {
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trigger(Event:Fwd_GETX, in_msg.Address);
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}
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} else if (in_msg.Type == CoherenceRequestType:GETS) {
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trigger(Event:Fwd_GETS, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:INV) {
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trigger(Event:Inv, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
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trigger(Event:Writeback_Ack, in_msg.Address);
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} else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
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trigger(Event:Writeback_Nack, in_msg.Address);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Response Network
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in_port(responseToCache_in, ResponseMsg, responseToCache) {
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if (responseToCache_in.isReady()) {
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peek(responseToCache_in, ResponseMsg) {
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if (in_msg.Type == CoherenceResponseType:ACK) {
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trigger(Event:Ack, in_msg.Address);
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} else if (in_msg.Type == CoherenceResponseType:DATA) {
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trigger(Event:Data, in_msg.Address);
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} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE_CLEAN) {
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trigger(Event:Exclusive_Data_Clean, in_msg.Address);
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} else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE_DIRTY) {
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trigger(Event:Exclusive_Data_Dirty, in_msg.Address);
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} else {
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error("Unexpected message");
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}
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}
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}
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}
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// Nothing from the unblock network
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// Mandatory Queue
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in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
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if (mandatoryQueue_in.isReady()) {
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peek(mandatoryQueue_in, CacheMsg) {
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// Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
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if (in_msg.Type == CacheRequestType:IFETCH) {
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// ** INSTRUCTION ACCESS ***
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// Check to see if it is in the OTHER L1
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if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
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// The block is in the wrong L1, try to write it to the L2
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if (L2cacheMemory.cacheAvail(in_msg.Address)) {
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trigger(Event:L1_to_L2, in_msg.Address);
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} else {
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
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}
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}
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if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
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// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
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} else {
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if (L1IcacheMemory.cacheAvail(in_msg.Address)) {
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// L1 does't have the line, but we have space for it in the L1
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if (L2cacheMemory.isTagPresent(in_msg.Address)) {
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// L2 has it (maybe not with the right permissions)
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trigger(Event:L2_to_L1I, in_msg.Address);
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} else {
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// We have room, the L2 doesn't have it, so the L1 fetches the line
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
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}
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} else {
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// No room in the L1, so we need to make room
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if (L2cacheMemory.cacheAvail(L1IcacheMemory.cacheProbe(in_msg.Address))) {
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// The L2 has room, so we move the line from the L1 to the L2
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trigger(Event:L1_to_L2, L1IcacheMemory.cacheProbe(in_msg.Address));
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} else {
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// The L2 does not have room, so we replace a line from the L2
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(L1IcacheMemory.cacheProbe(in_msg.Address)));
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}
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}
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}
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} else {
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// *** DATA ACCESS ***
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// Check to see if it is in the OTHER L1
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if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
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// The block is in the wrong L1, try to write it to the L2
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if (L2cacheMemory.cacheAvail(in_msg.Address)) {
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trigger(Event:L1_to_L2, in_msg.Address);
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} else {
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(in_msg.Address));
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}
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}
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if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
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// The tag matches for the L1, so the L1 fetches the line. We know it can't be in the L2 due to exclusion
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
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} else {
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if (L1DcacheMemory.cacheAvail(in_msg.Address)) {
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// L1 does't have the line, but we have space for it in the L1
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if (L2cacheMemory.isTagPresent(in_msg.Address)) {
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// L2 has it (maybe not with the right permissions)
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trigger(Event:L2_to_L1D, in_msg.Address);
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} else {
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// We have room, the L2 doesn't have it, so the L1 fetches the line
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trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
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}
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} else {
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// No room in the L1, so we need to make room
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if (L2cacheMemory.cacheAvail(L1DcacheMemory.cacheProbe(in_msg.Address))) {
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// The L2 has room, so we move the line from the L1 to the L2
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trigger(Event:L1_to_L2, L1DcacheMemory.cacheProbe(in_msg.Address));
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} else {
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// The L2 does not have room, so we replace a line from the L2
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trigger(Event:L2_Replacement, L2cacheMemory.cacheProbe(L1DcacheMemory.cacheProbe(in_msg.Address)));
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}
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}
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}
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}
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}
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}
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}
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// ACTIONS
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action(a_issueGETS, "a", desc="Issue GETS") {
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enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETS;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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// TBEs[address].NumPendingMsgs := numberOfNodes(); // One from each other processor (n-1) plus the memory (+1)
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}
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}
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action(b_issueGETX, "b", desc="Issue GETX") {
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enqueue(requestNetwork_out, RequestMsg, latency="(ISSUE_LATENCY-1)") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:GETX;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Request_Control;
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// TBEs[address].NumPendingMsgs := numberOfNodes(); // One from each other processor (n-1) plus the memory (+1)
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}
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}
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action(d_issuePUTX, "d", desc="Issue PUTX") {
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enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:PUTX;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(dd_issuePUTO, "\d", desc="Issue PUTO") {
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enqueue(requestNetwork_out, RequestMsg, latency="ISSUE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceRequestType:PUTO;
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out_msg.Requestor := machineID;
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out_msg.Destination.add(map_Address_to_Directory(address));
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out_msg.MessageSize := MessageSizeType:Writeback_Control;
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}
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}
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action(e_sendData, "e", desc="Send data from cache to requestor") {
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peek(forwardToCache_in, RequestMsg) {
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enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") {
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out_msg.Address := address;
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out_msg.Type := CoherenceResponseType:DATA;
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out_msg.Sender := machineID;
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out_msg.Destination.add(in_msg.Requestor);
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out_msg.DataBlk := getCacheEntry(address).DataBlk;
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out_msg.Dirty := getCacheEntry(address).Dirty;
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out_msg.Acks := in_msg.Acks;
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out_msg.MessageSize := MessageSizeType:Response_Data;
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}
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}
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}
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action(ee_sendDataExclusive, "\e", desc="Send data from cache to requestor, don't keep a shared copy") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE_DIRTY;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := getCacheEntry(address).DataBlk;
|
|
out_msg.Dirty := getCacheEntry(address).Dirty;
|
|
out_msg.Acks := in_msg.Acks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(f_sendAck, "f", desc="Send ack from cache to requestor") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:ACK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.Acks := 0 - 1; // -1
|
|
out_msg.MessageSize := MessageSizeType:Response_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(g_sendUnblock, "g", desc="Send unblock to memory") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency="NULL_LATENCY") {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:UNBLOCK;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
}
|
|
}
|
|
|
|
action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency="NULL_LATENCY") {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.MessageSize := MessageSizeType:Unblock_Control;
|
|
}
|
|
}
|
|
|
|
action(h_load_hit, "h", desc="Notify sequencer the load completed.") {
|
|
DEBUG_EXPR(getCacheEntry(address).DataBlk);
|
|
sequencer.readCallback(address, getCacheEntry(address).DataBlk);
|
|
}
|
|
|
|
action(hh_store_hit, "\h", desc="Notify sequencer that store completed.") {
|
|
DEBUG_EXPR(getCacheEntry(address).DataBlk);
|
|
sequencer.writeCallback(address, getCacheEntry(address).DataBlk);
|
|
getCacheEntry(address).Dirty := true;
|
|
}
|
|
|
|
action(i_allocateTBE, "i", desc="Allocate TBE") {
|
|
check_allocate(TBEs);
|
|
TBEs.allocate(address);
|
|
TBEs[address].DataBlk := getCacheEntry(address).DataBlk; // Data only used for writebacks
|
|
TBEs[address].Dirty := getCacheEntry(address).Dirty;
|
|
}
|
|
|
|
action(j_popTriggerQueue, "j", desc="Pop trigger queue.") {
|
|
triggerQueue_in.dequeue();
|
|
}
|
|
|
|
action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
|
|
mandatoryQueue_in.dequeue();
|
|
}
|
|
|
|
action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") {
|
|
forwardToCache_in.dequeue();
|
|
}
|
|
|
|
action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks;
|
|
}
|
|
}
|
|
|
|
action(mm_decrementNumberOfMessages, "\m", desc="Decrement the number of messages for which we're waiting") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
TBEs[address].NumPendingMsgs := TBEs[address].NumPendingMsgs - in_msg.Acks;
|
|
}
|
|
}
|
|
|
|
action(n_popResponseQueue, "n", desc="Pop response queue") {
|
|
responseToCache_in.dequeue();
|
|
}
|
|
|
|
action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") {
|
|
if (TBEs[address].NumPendingMsgs == 0) {
|
|
enqueue(triggerQueue_out, TriggerMsg) {
|
|
out_msg.Address := address;
|
|
out_msg.Type := TriggerType:ALL_ACKS;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(q_sendDataFromTBEToCache, "q", desc="Send data from TBE to cache") {
|
|
peek(forwardToCache_in, RequestMsg) {
|
|
enqueue(responseNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") {
|
|
out_msg.Address := address;
|
|
out_msg.Type := CoherenceResponseType:DATA;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(in_msg.Requestor);
|
|
out_msg.DataBlk := TBEs[address].DataBlk;
|
|
out_msg.Dirty := TBEs[address].Dirty;
|
|
out_msg.Acks := in_msg.Acks;
|
|
out_msg.MessageSize := MessageSizeType:Response_Data;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(qq_sendDataFromTBEToMemory, "\q", desc="Send data from TBE to memory") {
|
|
enqueue(unblockNetwork_out, ResponseMsg, latency="CACHE_RESPONSE_LATENCY") {
|
|
out_msg.Address := address;
|
|
out_msg.Sender := machineID;
|
|
out_msg.Destination.add(map_Address_to_Directory(address));
|
|
out_msg.Dirty := TBEs[address].Dirty;
|
|
if (TBEs[address].Dirty) {
|
|
out_msg.Type := CoherenceResponseType:WRITEBACK_DIRTY;
|
|
out_msg.DataBlk := TBEs[address].DataBlk;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Data;
|
|
} else {
|
|
out_msg.Type := CoherenceResponseType:WRITEBACK_CLEAN;
|
|
// NOTE: in a real system this would not send data. We send
|
|
// data here only so we can check it at the memory
|
|
out_msg.DataBlk := TBEs[address].DataBlk;
|
|
out_msg.MessageSize := MessageSizeType:Writeback_Control;
|
|
}
|
|
}
|
|
}
|
|
|
|
action(s_deallocateTBE, "s", desc="Deallocate TBE") {
|
|
TBEs.deallocate(address);
|
|
}
|
|
|
|
action(u_writeDataToCache, "u", desc="Write data to cache") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
getCacheEntry(address).DataBlk := in_msg.DataBlk;
|
|
getCacheEntry(address).Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(v_writeDataToCacheVerify, "v", desc="Write data to cache, assert it was same as before") {
|
|
peek(responseToCache_in, ResponseMsg) {
|
|
assert(getCacheEntry(address).DataBlk == in_msg.DataBlk);
|
|
getCacheEntry(address).DataBlk := in_msg.DataBlk;
|
|
getCacheEntry(address).Dirty := in_msg.Dirty;
|
|
}
|
|
}
|
|
|
|
action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") {
|
|
if (L1DcacheMemory.isTagPresent(address)) {
|
|
L1DcacheMemory.deallocate(address);
|
|
} else {
|
|
L1IcacheMemory.deallocate(address);
|
|
}
|
|
}
|
|
|
|
action(ii_allocateL1DCacheBlock, "\i", desc="Set L1 D-cache tag equal to tag of block B.") {
|
|
if (L1DcacheMemory.isTagPresent(address) == false) {
|
|
L1DcacheMemory.allocate(address);
|
|
}
|
|
}
|
|
|
|
action(jj_allocateL1ICacheBlock, "\j", desc="Set L1 I-cache tag equal to tag of block B.") {
|
|
if (L1IcacheMemory.isTagPresent(address) == false) {
|
|
L1IcacheMemory.allocate(address);
|
|
}
|
|
}
|
|
|
|
action(vv_allocateL2CacheBlock, "\v", desc="Set L2 cache tag equal to tag of block B.") {
|
|
L2cacheMemory.allocate(address);
|
|
}
|
|
|
|
action(rr_deallocateL2CacheBlock, "\r", desc="Deallocate L2 cache block. Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
|
|
L2cacheMemory.deallocate(address);
|
|
}
|
|
|
|
action(ss_copyFromL1toL2, "\s", desc="Copy data block from L1 (I or D) to L2") {
|
|
if (L1DcacheMemory.isTagPresent(address)) {
|
|
L2cacheMemory[address] := L1DcacheMemory[address];
|
|
} else {
|
|
L2cacheMemory[address] := L1IcacheMemory[address];
|
|
}
|
|
}
|
|
|
|
action(tt_copyFromL2toL1, "\t", desc="Copy data block from L2 to L1 (I or D)") {
|
|
if (L1DcacheMemory.isTagPresent(address)) {
|
|
L1DcacheMemory[address] := L2cacheMemory[address];
|
|
} else {
|
|
L1IcacheMemory[address] := L2cacheMemory[address];
|
|
}
|
|
}
|
|
|
|
action(uu_profileMiss, "\u", desc="Profile the demand miss") {
|
|
peek(mandatoryQueue_in, CacheMsg) {
|
|
profile_miss(in_msg, id);
|
|
}
|
|
}
|
|
|
|
action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") {
|
|
mandatoryQueue_in.recycle();
|
|
}
|
|
|
|
//*****************************************************
|
|
// TRANSITIONS
|
|
//*****************************************************
|
|
|
|
// Transitions for Load/Store/L2_Replacement from transient states
|
|
transition({IM, SM, OM, IS, OI, MI, II}, {Store, L2_Replacement}) {
|
|
zz_recycleMandatoryQueue;
|
|
}
|
|
|
|
transition({IM, IS, OI, MI, II}, {Load, Ifetch}) {
|
|
zz_recycleMandatoryQueue;
|
|
}
|
|
|
|
transition({IM, SM, OM, IS, OI, MI, II}, L1_to_L2) {
|
|
zz_recycleMandatoryQueue;
|
|
}
|
|
|
|
// Transitions moving data between the L1 and L2 caches
|
|
transition({I, S, O, E, M, MM}, L1_to_L2) {
|
|
vv_allocateL2CacheBlock;
|
|
ss_copyFromL1toL2; // Not really needed for state I
|
|
kk_deallocateL1CacheBlock;
|
|
}
|
|
|
|
transition({I, S, O, E, M, MM}, L2_to_L1D) {
|
|
ii_allocateL1DCacheBlock;
|
|
tt_copyFromL2toL1; // Not really needed for state I
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition({I, S, O, E, M, MM}, L2_to_L1I) {
|
|
jj_allocateL1ICacheBlock;
|
|
tt_copyFromL2toL1; // Not really needed for state I
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
// Transitions from Idle
|
|
transition({NP, I}, Load, IS) {
|
|
ii_allocateL1DCacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({NP, I}, Ifetch, IS) {
|
|
jj_allocateL1ICacheBlock;
|
|
i_allocateTBE;
|
|
a_issueGETS;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({NP, I}, Store, IM) {
|
|
ii_allocateL1DCacheBlock;
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(I, L2_Replacement) {
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition({NP, I}, Inv) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from Shared
|
|
transition({S, SM}, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, Store, SM) {
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(S, L2_Replacement, I) {
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(S, Inv, I) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from Owned
|
|
transition({O, OM}, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(O, Store, OM) {
|
|
i_allocateTBE;
|
|
b_issueGETX;
|
|
// p_decrementNumberOfMessagesByOne;
|
|
uu_profileMiss;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(O, L2_Replacement, OI) {
|
|
i_allocateTBE;
|
|
dd_issuePUTO;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(O, Fwd_GETX, I) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(O, Fwd_GETS) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from MM
|
|
transition(MM, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(MM, Store) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition(MM, L2_Replacement, MI) {
|
|
i_allocateTBE;
|
|
d_issuePUTX;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition(MM, Fwd_GETX, I) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MM, Fwd_GETS, I) {
|
|
ee_sendDataExclusive;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from M
|
|
transition({E, M}, {Load, Ifetch}) {
|
|
h_load_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({E, M}, Store, MM) {
|
|
hh_store_hit;
|
|
k_popMandatoryQueue;
|
|
}
|
|
|
|
transition({E, M}, L2_Replacement, MI) {
|
|
i_allocateTBE;
|
|
d_issuePUTX;
|
|
rr_deallocateL2CacheBlock;
|
|
}
|
|
|
|
transition({E, M}, Fwd_GETX, I) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({E, M}, Fwd_GETS, O) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from IM
|
|
|
|
transition(IM, Inv) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(IM, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IM, Data, OM) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
// Transitions from SM
|
|
transition(SM, Inv, IM) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(SM, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(SM, Data, OM) {
|
|
v_writeDataToCacheVerify;
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
// Transitions from OM
|
|
transition(OM, Own_GETX) {
|
|
mm_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM, Fwd_GETX, IM) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM, Fwd_GETS, OM) {
|
|
e_sendData;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OM, Ack) {
|
|
m_decrementNumberOfMessages;
|
|
o_checkForCompletion;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(OM, All_acks, MM) {
|
|
hh_store_hit;
|
|
gg_sendUnblockExclusive;
|
|
s_deallocateTBE;
|
|
j_popTriggerQueue;
|
|
}
|
|
|
|
// Transitions from IS
|
|
|
|
transition(IS, Inv) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(IS, Data, S) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
h_load_hit;
|
|
g_sendUnblock;
|
|
s_deallocateTBE;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IS, Exclusive_Data_Clean, E) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
h_load_hit;
|
|
gg_sendUnblockExclusive;
|
|
s_deallocateTBE;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
transition(IS, Exclusive_Data_Dirty, M) {
|
|
u_writeDataToCache;
|
|
m_decrementNumberOfMessages;
|
|
h_load_hit;
|
|
gg_sendUnblockExclusive;
|
|
s_deallocateTBE;
|
|
n_popResponseQueue;
|
|
}
|
|
|
|
// Transitions from OI/MI
|
|
|
|
transition(MI, Fwd_GETS) {
|
|
q_sendDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MI, Fwd_GETX, II) {
|
|
q_sendDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OI, Fwd_GETS) {
|
|
q_sendDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(OI, Fwd_GETX, II) {
|
|
q_sendDataFromTBEToCache;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition({OI, MI}, Writeback_Ack, I) {
|
|
qq_sendDataFromTBEToMemory;
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(MI, Writeback_Nack, OI) {
|
|
// FIXME: This might cause deadlock by re-using the writeback
|
|
// channel, we should handle this case differently.
|
|
dd_issuePUTO;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
// Transitions from II
|
|
transition(II, Writeback_Ack, I) {
|
|
g_sendUnblock;
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(II, Writeback_Nack, I) {
|
|
s_deallocateTBE;
|
|
l_popForwardQueue;
|
|
}
|
|
|
|
transition(II, Inv) {
|
|
f_sendAck;
|
|
l_popForwardQueue;
|
|
}
|
|
}
|
|
|