gem5/tests/configs/realview-o3-checker.py
Andreas Hansson 651de2d9af config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
2012-10-26 06:42:42 -04:00

71 lines
3 KiB
Python

# Copyright (c) 2011 ARM Limited
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# Authors: Geoffrey Blake
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
import FSConfig
from Caches import *
#cpu
cpu = DerivO3CPU(cpu_id=0)
#the system
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
system.cpu = cpu
#connect up the checker
cpu.addCheckerCpu()
#create the iocache
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
system.iocache.cpu_side = system.iobus.master
system.iocache.mem_side = system.membus.slave
#connect up the cpu and caches
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4),
L2Cache(size = '4MB', assoc = 8))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu and caches to the rest of the system
cpu.connectAllPorts(system.membus)
# set the cpu clock along with the caches and l1-l2 bus
cpu.clock = '2GHz'
root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('1THz')