Steve Reinhardt 58c29640b7 Add a new operation class for IPR accesses, and have IPR-accessing ... instructions use it (instead of IntALU, as before). Default config has a single non-pipelined 3-cycle unit. A bit conservative for the ev6 (some are 1, some are 3). arch/alpha/isa_desc: Make hw_mfpr and hw_mtpr use IprAccessOp op class. cpu/full_cpu/op_class.hh: Add IprAccess. --HG-- extra : convert_revision : d4103da3343a586936839e29981fd15d6930d442		2005-03-01 00:39:57 -05:00
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alpha	Add a new operation class for IPR accesses, and have IPR-accessing	2005-03-01 00:39:57 -05:00
isa_parser.py	Add support for CPU models to execute the effective	2005-02-03 20:47:11 -05:00