74553c7d3f
This patch updates the stats to reflect the addition of the bus stats, and changes to the bus layers. In addition it updates the stats to match the addition of the static pipeline latency of the memory conotroller and the addition of a stat tracking the bytes per activate.
105 lines
11 KiB
Text
105 lines
11 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.861538 # Number of seconds simulated
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sim_ticks 861538200000 # Number of ticks simulated
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final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 2812355 # Simulator instruction rate (inst/s)
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host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 1568696760 # Simulator tick rate (ticks/s)
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host_mem_usage 234512 # Number of bytes of host memory used
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host_seconds 549.21 # Real time elapsed on the host
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sim_insts 1544563041 # Number of instructions simulated
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sim_ops 1723073853 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
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system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
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system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 482384187 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 2026949776 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 7171199554 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 1835539818 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 9006739373 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 7171199554 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 7171199554 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu.data 724469782 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 724469782 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 7171199554 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 2560009600 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 9731209155 # Total bandwidth to/from this memory (bytes/s)
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system.membus.throughput 9731209155 # Throughput (bytes/s)
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system.membus.data_through_bus 8383808419 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.cpu.dtb.inst_hits 0 # ITB inst hits
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system.cpu.dtb.inst_misses 0 # ITB inst misses
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system.cpu.dtb.read_hits 0 # DTB read hits
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system.cpu.dtb.read_misses 0 # DTB read misses
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system.cpu.dtb.write_hits 0 # DTB write hits
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system.cpu.dtb.write_misses 0 # DTB write misses
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system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.dtb.read_accesses 0 # DTB read accesses
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system.cpu.dtb.write_accesses 0 # DTB write accesses
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system.cpu.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.itb.inst_hits 0 # ITB inst hits
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system.cpu.itb.inst_misses 0 # ITB inst misses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
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system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
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system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
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system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
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system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
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system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.inst_accesses 0 # ITB inst accesses
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system.cpu.itb.hits 0 # DTB hits
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system.cpu.itb.misses 0 # DTB misses
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system.cpu.itb.accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 46 # Number of system calls
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system.cpu.numCycles 1723076401 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.committedInsts 1544563041 # Number of instructions committed
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system.cpu.committedOps 1723073853 # Number of ops (including micro ops) committed
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system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses
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system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
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system.cpu.num_func_calls 27330256 # number of times a function call or return occured
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system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls
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system.cpu.num_int_insts 1536941842 # number of integer instructions
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system.cpu.num_fp_insts 36 # number of float instructions
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system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read
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system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written
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system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
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system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu.num_mem_refs 660773815 # number of memory refs
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system.cpu.num_load_insts 485926769 # Number of load instructions
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system.cpu.num_store_insts 174847046 # Number of store instructions
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system.cpu.num_idle_cycles 0 # Number of idle cycles
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system.cpu.num_busy_cycles 1723076401 # Number of busy cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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---------- End Simulation Statistics ----------
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