3cf733bcc0
This patch unifies the full-system regression config scripts and uses the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up the L1s and L2, and create the bus inbetween. The patch is a step on the way to use the clock period to express the cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2 bus, and these modules thus use the CPU clock. The patch does not change the value of any stats, but plenty names, and a follow-up patch contains the update to the stats, chaning system.l2c to system.cpu.l2cache.
98 lines
3.1 KiB
Python
98 lines
3.1 KiB
Python
# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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import FSConfig
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# --------------------
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# Base L1 Cache
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# ====================
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class L1(BaseCache):
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hit_latency = '1ns'
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response_latency = '1ns'
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block_size = 64
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mshrs = 4
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tgts_per_mshr = 8
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is_top_level = True
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# ----------------------
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# Base L2 Cache
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# ----------------------
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class L2(BaseCache):
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block_size = 64
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hit_latency = '10ns'
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response_latency = '10ns'
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mshrs = 92
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tgts_per_mshr = 16
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write_buffers = 8
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# ---------------------
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# I/O Cache
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# ---------------------
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class IOCache(BaseCache):
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assoc = 8
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block_size = 64
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hit_latency = '50ns'
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response_latency = '50ns'
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mshrs = 20
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size = '1kB'
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tgts_per_mshr = 12
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addr_ranges = [AddrRange(0, size='256MB')]
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forward_snoops = False
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#cpu
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cpu = AtomicSimpleCPU(cpu_id=0)
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#the system
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system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
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system.cpu = cpu
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#create the iocache
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system.iocache = IOCache()
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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#connect up the cpu and caches
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cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
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L1(size = '32kB', assoc = 4),
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L2(size = '4MB', assoc = 8))
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# create the interrupt controller
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cpu.createInterruptController()
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# connect cpu and caches to the rest of the system
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cpu.connectAllPorts(system.membus)
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# set the cpu clock along with the caches and l1-l2 bus
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cpu.clock = '2GHz'
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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