b63631536d
This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size.
646 lines
74 KiB
Text
646 lines
74 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000025 # Number of seconds simulated
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sim_ticks 25046000 # Number of ticks simulated
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final_tick 25046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 22373 # Simulator instruction rate (inst/s)
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host_op_rate 22372 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 87684145 # Simulator tick rate (ticks/s)
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host_mem_usage 225308 # Number of bytes of host memory used
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host_seconds 0.29 # Real time elapsed on the host
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sim_insts 6390 # Number of instructions simulated
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sim_ops 6390 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
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system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu.inst 766589475 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 429290106 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 1195879582 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 766589475 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 766589475 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 766589475 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 429290106 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 1195879582 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 469 # Total number of read requests accepted by DRAM controller
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system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller
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system.physmem.readBursts 469 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
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system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
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system.physmem.bytesRead 29952 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 29952 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q
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system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 29 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 27 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 47 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 41 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 19 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 3 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 1 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 19 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 15 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 119 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 46 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 12 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 25031500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 469 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 318 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 67 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 285.611940 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 145.316634 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 484.514157 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::64 33 49.25% 49.25% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128 8 11.94% 61.19% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::192 5 7.46% 68.66% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256 5 7.46% 76.12% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::320 4 5.97% 82.09% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384 3 4.48% 86.57% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::448 1 1.49% 88.06% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512 1 1.49% 89.55% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::704 1 1.49% 91.04% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768 1 1.49% 92.54% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::832 1 1.49% 94.03% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1344 1 1.49% 95.52% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1856 1 1.49% 97.01% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2368 1 1.49% 98.51% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::2496 1 1.49% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 67 # Bytes accessed per row activation
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system.physmem.totQLat 1857500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 11820000 # Sum of mem lat for all requests
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system.physmem.totBusLat 2345000 # Total cycles spent in databus access
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system.physmem.totBankLat 7617500 # Total cycles spent in bank access
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system.physmem.avgQLat 3960.55 # Average queueing delay per request
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system.physmem.avgBankLat 16242.00 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 25202.56 # Average memory access latency
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system.physmem.avgRdBW 1195.88 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 1195.88 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 9.34 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.47 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 402 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 85.71 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 53372.07 # Average gap between requests
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system.membus.throughput 1195879582 # Throughput (bytes/s)
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system.membus.trans_dist::ReadReq 396 # Transaction distribution
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system.membus.trans_dist::ReadResp 395 # Transaction distribution
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system.membus.trans_dist::ReadExReq 73 # Transaction distribution
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system.membus.trans_dist::ReadExResp 73 # Transaction distribution
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes)
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system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
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system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
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system.membus.data_through_bus 29952 # Total data (bytes)
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system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
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system.membus.reqLayer0.occupancy 559000 # Layer occupancy (ticks)
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system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
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system.membus.respLayer1.occupancy 4378000 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 17.5 # Layer utilization (%)
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system.cpu.branchPred.lookups 1632 # Number of BP lookups
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system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
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system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
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system.cpu.branchPred.BTBLookups 1266 # Number of BTB lookups
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system.cpu.branchPred.BTBHits 352 # Number of BTB hits
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system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.branchPred.BTBHitPct 27.804107 # BTB Hit Percentage
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system.cpu.branchPred.usedRAS 126 # Number of times the RAS was used to get a target.
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system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 1184 # DTB read hits
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system.cpu.dtb.read_misses 7 # DTB read misses
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system.cpu.dtb.read_acv 0 # DTB read access violations
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system.cpu.dtb.read_accesses 1191 # DTB read accesses
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system.cpu.dtb.write_hits 893 # DTB write hits
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system.cpu.dtb.write_misses 3 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 896 # DTB write accesses
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system.cpu.dtb.data_hits 2077 # DTB hits
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system.cpu.dtb.data_misses 10 # DTB misses
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system.cpu.dtb.data_acv 0 # DTB access violations
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system.cpu.dtb.data_accesses 2087 # DTB accesses
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system.cpu.itb.fetch_hits 915 # ITB hits
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system.cpu.itb.fetch_misses 17 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 932 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 17 # Number of system calls
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system.cpu.numCycles 50093 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
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system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
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system.cpu.regfile_manager.intRegFileReads 5174 # Number of Reads from Int. Register File
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system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
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system.cpu.regfile_manager.intRegFileAccesses 9741 # Total Accesses (Read+Write) to the Int. Register File
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system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
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system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
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system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
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system.cpu.regfile_manager.regForwards 2976 # Number of Registers Read Through Forwarding Logic
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system.cpu.agen_unit.agens 2152 # Number of Address Generations
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system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
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system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
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system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted
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system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts
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system.cpu.execution_unit.executions 4448 # Number of Instructions Executed.
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system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
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system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
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system.cpu.contextSwitches 1 # Number of context switches
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system.cpu.threadCycles 11606 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
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system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
|
|
system.cpu.timesIdled 460 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 42717 # Number of cycles cpu's stages were not processed
|
|
system.cpu.runCycles 7376 # Number of cycles cpu stages are processed.
|
|
system.cpu.activity 14.724612 # Percentage of cycles cpu is active
|
|
system.cpu.comLoads 1183 # Number of Load instructions committed
|
|
system.cpu.comStores 865 # Number of Store instructions committed
|
|
system.cpu.comBranches 1050 # Number of Branches instructions committed
|
|
system.cpu.comNops 17 # Number of Nop instructions committed
|
|
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
|
|
system.cpu.comInts 3254 # Number of Integer instructions committed
|
|
system.cpu.comFloats 2 # Number of Floating Point instructions committed
|
|
system.cpu.committedInsts 6390 # Number of Instructions committed (Per-Thread)
|
|
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
|
|
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
|
|
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
|
|
system.cpu.cpi 7.839280 # CPI: Cycles Per Instruction (Per-Thread)
|
|
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
|
|
system.cpu.cpi_total 7.839280 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 0.127563 # IPC: Instructions Per Cycle (Per-Thread)
|
|
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
|
|
system.cpu.ipc_total 0.127563 # IPC: Total IPC of All Threads
|
|
system.cpu.stage0.idleCycles 45169 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage0.utilization 9.829717 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage1.idleCycles 46200 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage1.utilization 7.771545 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage2.idleCycles 45932 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage2.utilization 8.306550 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage3.idleCycles 48759 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage3.runCycles 1334 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage3.utilization 2.663047 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.stage4.idleCycles 45635 # Number of cycles 0 instructions are processed.
|
|
system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed.
|
|
system.cpu.stage4.utilization 8.899447 # Percentage of cycles stage was utilized (processing insts).
|
|
system.cpu.icache.tags.replacements 0 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 141.294375 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 141.294375 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.068991 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.068991 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 560 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 355 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24600000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 24600000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 24600000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 24600000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 24600000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 24600000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69295.774648 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 69295.774648 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 69295.774648 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 69295.774648 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 69295.774648 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20800250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 20800250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20800250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 20800250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20800250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 20800250 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68875 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68875 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68875 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 68875 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 1198434880 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 512750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 278750 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 0 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 197.784355 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.343624 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.440731 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001722 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.006036 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20481750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6961500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 27443250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4890250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4890250 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 20481750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 11851750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 32333500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 20481750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 11851750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 32333500 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68045.681063 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73278.947368 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69301.136364 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66989.726027 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66989.726027 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 68941.364606 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68045.681063 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70546.130952 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 68941.364606 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16699250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5777500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22476750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3986750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3986750 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16699250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9764250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 26463500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16699250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9764250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 26463500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55479.235880 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60815.789474 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56759.469697 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54613.013699 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54613.013699 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55479.235880 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58120.535714 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56425.373134 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 0 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 103.103023 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 103.103023 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.025172 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.025172 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 1601 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 447 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7410000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7410000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 21312750 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 21312750 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 28722750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 28722750 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 28722750 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 28722750 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76391.752577 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 76391.752577 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60893.571429 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 60893.571429 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 64256.711409 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 64256.711409 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 64256.711409 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 496 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.533333 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7063000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7063000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4967750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4967750 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 12030750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 12030750 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74347.368421 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74347.368421 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68051.369863 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68051.369863 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71611.607143 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71611.607143 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|