e7f442d527
Ignoring returned latency for now. Refactored loadSections in ObjectFile hierarchy. base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.hh: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. base/loader/object_file.cc: Have each section record a pointer to image data. This allows us to move common loadSections code into ObjectFile. Also explicitly load BSS now since we need to allocate the translations for it in syscall emulation. cpu/base.hh: Don't need memPort (just pass port in to ExecContext constructor). cpu/exec_context.cc: cpu/exec_context.hh: mem/port.cc: mem/translating_port.cc: mem/translating_port.hh: Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.cc: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Several more minor bug fixes. Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now. Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all). Pass syscall emulation Port into constructor instead of getting it from BaseCPU. cpu/simple/cpu.hh: Explicitly choose one of three timing models. Statically allocate request and packet objects when possible. Pass syscall emulation Port into constructor instead of getting it from BaseCPU. mem/physical.cc: Set packet result field. --HG-- extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
385 lines
11 KiB
C++
385 lines
11 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
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#define __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
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#include "base/statistics.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/sampler/sampler.hh"
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#include "cpu/static_inst.hh"
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#include "mem/packet.hh"
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#include "mem/port.hh"
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#include "mem/request.hh"
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#include "sim/eventq.hh"
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// forward declarations
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#if FULL_SYSTEM
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class Processor;
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class AlphaITB;
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class AlphaDTB;
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class Memory;
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class RemoteGDB;
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class GDBListener;
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#else
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class Process;
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#endif // FULL_SYSTEM
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class MemInterface;
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class Checkpoint;
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namespace Trace {
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class InstRecord;
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}
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// Set exactly one of these symbols to 1 to set the memory access
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// model. Probably should make these template parameters, or even
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// just fork the CPU models.
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//
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#define SIMPLE_CPU_MEM_TIMING 0
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#define SIMPLE_CPU_MEM_ATOMIC 0
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#define SIMPLE_CPU_MEM_IMMEDIATE 1
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class SimpleCPU : public BaseCPU
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{
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class CpuPort : public Port
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{
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SimpleCPU *cpu;
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public:
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CpuPort(SimpleCPU *_cpu)
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: cpu(_cpu)
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{ }
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protected:
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virtual bool recvTiming(Packet &pkt);
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virtual Tick recvAtomic(Packet &pkt);
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virtual void recvFunctional(Packet &pkt);
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virtual void recvStatusChange(Status status);
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virtual Packet *recvRetry();
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};
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CpuPort icachePort;
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CpuPort dcachePort;
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public:
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// main simulation loop (one cycle)
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void tick();
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private:
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struct TickEvent : public Event
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{
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SimpleCPU *cpu;
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int width;
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TickEvent(SimpleCPU *c, int w);
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int numCycles)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + cycles(numCycles));
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + cycles(numCycles));
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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private:
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Trace::InstRecord *traceData;
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public:
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//
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enum Status {
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Running,
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Idle,
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IcacheRetry,
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IcacheWaitResponse,
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IcacheAccessComplete,
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DcacheRetry,
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DcacheWaitResponse,
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DcacheWaitSwitch,
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SwitchedOut
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};
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private:
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Status _status;
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public:
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void post_interrupt(int int_num, int index);
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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public:
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struct Params : public BaseCPU::Params
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{
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int width;
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#if FULL_SYSTEM
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AlphaITB *itb;
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AlphaDTB *dtb;
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#else
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Memory *mem;
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Process *process;
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#endif
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};
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SimpleCPU(Params *params);
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virtual ~SimpleCPU();
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public:
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// execution context
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ExecContext *xc;
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void switchOut(Sampler *s);
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void takeOverFrom(BaseCPU *oldCPU);
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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#endif
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// current instruction
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MachInst inst;
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#if SIMPLE_CPU_MEM_TIMING
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Packet *retry_pkt;
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#elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
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CpuRequest *ifetch_req;
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Packet *ifetch_pkt;
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CpuRequest *data_read_req;
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Packet *data_read_pkt;
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CpuRequest *data_write_req;
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Packet *data_write_pkt;
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#endif
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// Pointer to the sampler that is telling us to switchover.
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// Used to signal the completion of the pipe drain and schedule
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// the next switchover
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Sampler *sampler;
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StaticInstPtr<TheISA> curStaticInst;
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Status status() const { return _status; }
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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virtual void deallocateContext(int thread_num);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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Counter numInst;
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Counter startNumInst;
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Stats::Scalar<> numInsts;
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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// number of simulated memory references
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Stats::Scalar<> numMemRefs;
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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// number of cycles stalled for I-cache responses
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Stats::Scalar<> icacheStallCycles;
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Counter lastIcacheStall;
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// number of cycles stalled for I-cache retries
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Stats::Scalar<> icacheRetryCycles;
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Counter lastIcacheRetry;
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// number of cycles stalled for D-cache responses
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Stats::Scalar<> dcacheStallCycles;
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Counter lastDcacheStall;
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// number of cycles stalled for D-cache retries
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Stats::Scalar<> dcacheRetryCycles;
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Counter lastDcacheRetry;
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void sendIcacheRequest(Packet *pkt);
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void sendDcacheRequest(Packet *pkt);
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void processResponse(Packet &response);
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Packet * processRetry();
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void recvStatusChange(Port::Status status) {}
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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template <class T>
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Fault read(Addr addr, T &data, unsigned flags);
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template <class T>
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Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
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// These functions are only used in CPU models that split
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// effective address computation from the actual memory access.
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void setEA(Addr EA) { panic("SimpleCPU::setEA() not implemented\n"); }
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Addr getEA() { panic("SimpleCPU::getEA() not implemented\n"); }
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size, unsigned flags)
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{
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// need to do this...
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}
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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// The register accessor methods provide the index of the
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// instruction's operand (e.g., 0 or 1), not the architectural
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// register index, to simplify the implementation of register
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// renaming. We find the architectural register index by indexing
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// into the instruction's own operand index table. Note that a
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// raw pointer to the StaticInst is provided instead of a
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// ref-counted StaticInstPtr to redice overhead. This is fine as
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// long as these methods don't copy the pointer into any long-term
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// storage (which is pretty hard to imagine they would have reason
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// to do).
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uint64_t readIntReg(const StaticInst<TheISA> *si, int idx)
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{
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return xc->readIntReg(si->srcRegIdx(idx));
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}
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float readFloatRegSingle(const StaticInst<TheISA> *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegSingle(reg_idx);
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}
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double readFloatRegDouble(const StaticInst<TheISA> *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegDouble(reg_idx);
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}
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uint64_t readFloatRegInt(const StaticInst<TheISA> *si, int idx)
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{
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int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
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return xc->readFloatRegInt(reg_idx);
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}
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void setIntReg(const StaticInst<TheISA> *si, int idx, uint64_t val)
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{
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xc->setIntReg(si->destRegIdx(idx), val);
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}
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void setFloatRegSingle(const StaticInst<TheISA> *si, int idx, float val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegSingle(reg_idx, val);
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}
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void setFloatRegDouble(const StaticInst<TheISA> *si, int idx, double val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegDouble(reg_idx, val);
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}
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void setFloatRegInt(const StaticInst<TheISA> *si, int idx, uint64_t val)
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{
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int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
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xc->setFloatRegInt(reg_idx, val);
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}
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uint64_t readPC() { return xc->readPC(); }
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void setNextPC(uint64_t val) { xc->setNextPC(val); }
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uint64_t readUniq() { return xc->readUniq(); }
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void setUniq(uint64_t val) { xc->setUniq(val); }
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uint64_t readFpcr() { return xc->readFpcr(); }
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void setFpcr(uint64_t val) { xc->setFpcr(val); }
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#if FULL_SYSTEM
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uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
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Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
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Fault hwrei() { return xc->hwrei(); }
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int readIntrFlag() { return xc->readIntrFlag(); }
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void setIntrFlag(int val) { xc->setIntrFlag(val); }
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bool inPalMode() { return xc->inPalMode(); }
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void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
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bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
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#else
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void syscall() { xc->syscall(); }
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#endif
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bool misspeculating() { return xc->misspeculating(); }
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ExecContext *xcBase() { return xc; }
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};
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#endif // __CPU_SIMPLE_CPU_SIMPLE_CPU_HH__
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