Ignoring returned latency for now.
Refactored loadSections in ObjectFile hierarchy.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
Have each section record a pointer to image data.
This allows us to move common loadSections code into ObjectFile.
base/loader/object_file.cc:
Have each section record a pointer to image data.
This allows us to move common loadSections code into ObjectFile.
Also explicitly load BSS now since we need to allocate the
translations for it in syscall emulation.
cpu/base.hh:
Don't need memPort (just pass port in to ExecContext constructor).
cpu/exec_context.cc:
cpu/exec_context.hh:
mem/port.cc:
mem/translating_port.cc:
mem/translating_port.hh:
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
cpu/simple/cpu.cc:
Explicitly choose one of three timing models.
Statically allocate request and packet objects when possible.
Several more minor bug fixes.
Works for simple program with SIMPLE_CPU_MEM_IMMEDIATE model now.
Probably have memory leaks with SIMPLE_CPU_MEM_TIMING (if it works at all).
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
cpu/simple/cpu.hh:
Explicitly choose one of three timing models.
Statically allocate request and packet objects when possible.
Pass syscall emulation Port into constructor instead of
getting it from BaseCPU.
mem/physical.cc:
Set packet result field.
--HG--
extra : convert_revision : 359d0ebe4b4665867f4e26e7394ec0f1d17cfc26
Ready to start testing if I could fix the linking errors I can't ever seem to fix.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add connecting of ports until builder can handle it.
mem/physical.cc:
Add function to allocate a port in the object
Remove some full_sys stuff untill needed
mem/physical.hh:
Add function to allocate a port in the object
python/m5/objects/BaseCPU.py:
Update the params
sim/process.cc:
Make sure to use the right name (hopefully CPU constructor already called)
--HG--
extra : convert_revision : 4089caf20d7eb53e5463c8ac93ddce5e43ea5d85
clean up implementation a little.
SConscript:
Add mem/port.cc
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move read/writeBlob functions to base Port class.
mem/port.hh:
Implement read/writeBlob functions.
No need for them to be virtual since the proxy
object (now called TranslatingPort) is not a
subclass of Port.
mem/port.cc:
Implement read/writeBlob functions.
--HG--
extra : convert_revision : a3660eaa43a7c286aca962f17fa32fbd42bf1fa6
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Add read/write blob definitions, still need to break it up into blk size chunks (where was the code stever wrote for that?)
mem/physical.hh:
Remove un-needed function (I think)
mem/port.hh:
Default these virtual functions to panic unimplented
mem/translating_port.cc:
Again handling read/write string properly.
Need the stever code to break things into page size chunks yet
mem/translating_port.hh:
Having trouble with the const declerator. I will need to read how it works, for now it compiles if I remove it.
--HG--
extra : convert_revision : f174e06700daa9967958d18e01798270c90d6dac
Now I need to fix linking errors, probably due to missing function details in new memory objects.
cpu/exec_context.cc:
cpu/exec_context.hh:
Fix constructor for SE mode
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Fix compilation errors
--HG--
extra : convert_revision : 6a58c0906340e10b654369c36f528fc17e3f19be
fixing things, partly by ignoring CPU models
that don't currently compile.
SConscript:
Split sources for fast, simple, and o3 CPU models into
separate source lists. For now none of these are included
in the base source list, so you won't get any CPU models
at all... but we still can't compile the other stuff so
it's not an issue.
Also get rid of obsolete encumbered/mem file.
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
cpu/exec_context.cc:
sim/process.cc:
sim/system.cc:
sim/system.hh:
FunctionalMemory -> Memory
cpu/pc_event.hh:
Get rid of unused badpc.
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
Move Port functions into .cc file.
mem/port.hh:
Make recvAddressRangesQuery panic by default instead
of being abstract... do CPUs need to implement this?
mem/request.hh:
Add prefetch flags.
sim/syscall_emul.hh:
Start to fix...
--HG--
extra : convert_revision : ece53b3855f20916caaa381598ac37e8c7adfba7
cpu/simple/cpu.cc:
Update for new memory system. Supports using ports to access the memory system. The IcacheMissStall/DcacheMissStall statuses have been changed to reflect the cache returning a response after a variable latency (due to hit/miss). They are now DcacheWaitResponse/IcacheWaitResponse. Also supports retrying accesses.
For now the body of the copy functions are commented out.
cpu/simple/cpu.hh:
Update for new memory system.
--HG--
extra : convert_revision : 5a80247537d98ed690f7b6119094d9f59b4c7d73
cpu/simple/cpu.cc:
Initialize the ports, also add Request and Packet instead of MemReq. Initial work at ICache read in place.
cpu/simple/cpu.hh:
Need to call the completion handler when we see a recieve.
--HG--
extra : convert_revision : a52caee6f0ceb5d9ee1e5acca63a202f5ea71359
cpu/simple/cpu.hh:
Some needed includes
mem/port.hh:
Now we removed the sendResult and replaced with void,tick,bool don't need it defined anymore
--HG--
extra : convert_revision : aea08ec299c41b9f9a5b0da7649cef0459315139
cpu/simple/cpu.hh:
Adding port definitions to simple cpu, still needs work.
mem/bus.hh:
no return for void functions
--HG--
extra : convert_revision : 42e5bc16af187d3a46eb25a15b600a8a11b88cc5
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line. Build option flags are now always
defined to 0 or 1, so checks must use '#if' rather than
'#ifdef'.
SConscript:
MySQL detection moved to SConstruct.
Add config/*.hh files (via ConfigFile builder).
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/ev5.hh:
arch/alpha/isa_traits.hh:
base/fast_alloc.hh:
base/statistics.cc:
base/statistics.hh:
base/stats/events.cc:
base/stats/events.hh:
cpu/base.cc:
cpu/base.hh:
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
cpu/o3/alpha_cpu_builder.cc:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/alpha_params.hh:
cpu/o3/commit_impl.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/fetch_impl.hh:
cpu/o3/iew.hh:
cpu/o3/iew_impl.hh:
cpu/o3/regfile.hh:
cpu/o3/rename_impl.hh:
cpu/o3/rob_impl.hh:
cpu/ozone/cpu.hh:
cpu/pc_event.cc:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
arch/alpha/isa_desc:
Convert compile flags from def/undef to 0/1.
Set via #include config/*.hh instead of command line.
Revamp fenv.h support... most of the ugliness is hidden
in base/fenv.hh now.
base/mysql.hh:
Fix typo in #ifndef guard.
build/SConstruct:
Build options are set via a build_options file in the
build directory instead of being inferred from the name
of the build directory.
Options are passed to C++ via config/*.hh files instead of
via the command line.
python/SConscript:
Generate m5_build_env directly from scons options
instead of indirectly via CPPDEFINES.
python/m5/convert.py:
Allow '0' and '1' for booleans.
Rewrite toBool to use dict.
base/fenv.hh:
Revamp <fenv.h> support to make it a compile option
(so we can test w/o it even if it's present) and to
make isa_desc cleaner.
--HG--
extra : convert_revision : 8f97dc11185bef5e1865b3269c7341df8525c9ad
