3a1428365a
readBytes and writeBytes had the word "bytes" in their names because they accessed blobs of bytes. This distinguished them from the read and write functions which handled higher level data types. Because those functions don't exist any more, this change renames readBytes and writeBytes to more general names, readMem and writeMem, which reflect the fact that they are how you read and write memory. This also makes their names more consistent with the register reading/writing functions, although those are still read and set for some reason.
299 lines
8.4 KiB
C++
299 lines
8.4 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Steve Reinhardt
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*/
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#ifndef __CPU_SIMPLE_TIMING_HH__
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#define __CPU_SIMPLE_TIMING_HH__
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#include "cpu/simple/base.hh"
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#include "cpu/translation.hh"
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#include "params/TimingSimpleCPU.hh"
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class TimingSimpleCPU : public BaseSimpleCPU
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{
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public:
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TimingSimpleCPU(TimingSimpleCPUParams * params);
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virtual ~TimingSimpleCPU();
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virtual void init();
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public:
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Event *drainEvent;
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private:
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/*
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* If an access needs to be broken into fragments, currently at most two,
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* the the following two classes are used as the sender state of the
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* packets so the CPU can keep track of everything. In the main packet
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* sender state, there's an array with a spot for each fragment. If a
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* fragment has already been accepted by the CPU, aka isn't waiting for
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* a retry, it's pointer is NULL. After each fragment has successfully
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* been processed, the "outstanding" counter is decremented. Once the
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* count is zero, the entire larger access is complete.
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*/
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class SplitMainSenderState : public Packet::SenderState
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{
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public:
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int outstanding;
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PacketPtr fragments[2];
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int
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getPendingFragment()
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{
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if (fragments[0]) {
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return 0;
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} else if (fragments[1]) {
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return 1;
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} else {
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return -1;
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}
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}
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};
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class SplitFragmentSenderState : public Packet::SenderState
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{
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public:
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SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
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bigPkt(_bigPkt), index(_index)
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{}
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PacketPtr bigPkt;
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int index;
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void
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clearFromParent()
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{
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SplitMainSenderState * main_send_state =
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dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
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main_send_state->fragments[index] = NULL;
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}
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};
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class FetchTranslation : public BaseTLB::Translation
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{
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protected:
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TimingSimpleCPU *cpu;
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public:
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FetchTranslation(TimingSimpleCPU *_cpu)
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: cpu(_cpu)
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{}
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void
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markDelayed()
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{
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assert(cpu->_status == Running);
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cpu->_status = ITBWaitResponse;
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}
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void
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finish(Fault fault, RequestPtr req, ThreadContext *tc,
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BaseTLB::Mode mode)
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{
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cpu->sendFetch(fault, req, tc);
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}
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};
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FetchTranslation fetchTranslation;
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void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
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void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read);
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void translationFault(Fault fault);
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void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
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void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
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RequestPtr req1, RequestPtr req2, RequestPtr req,
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uint8_t *data, bool read);
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bool handleReadPacket(PacketPtr pkt);
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// This function always implicitly uses dcache_pkt.
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bool handleWritePacket();
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class CpuPort : public Port
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{
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protected:
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TimingSimpleCPU *cpu;
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Tick lat;
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public:
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CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
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: Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
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{ }
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bool snoopRangeSent;
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protected:
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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virtual void recvStatusChange(Status status);
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virtual void getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop)
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{ resp.clear(); snoop = false; }
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struct TickEvent : public Event
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{
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PacketPtr pkt;
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TimingSimpleCPU *cpu;
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CpuPort *port;
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TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
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const char *description() const { return "Timing CPU tick"; }
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void schedule(PacketPtr _pkt, Tick t);
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};
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EventWrapper<Port, &Port::sendRetry> retryEvent;
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};
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class IcachePort : public CpuPort
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{
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public:
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IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
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: CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
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{ }
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protected:
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virtual bool recvTiming(PacketPtr pkt);
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virtual void recvRetry();
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struct ITickEvent : public TickEvent
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{
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ITickEvent(TimingSimpleCPU *_cpu)
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: TickEvent(_cpu) {}
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void process();
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const char *description() const { return "Timing CPU icache tick"; }
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};
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ITickEvent tickEvent;
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};
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class DcachePort : public CpuPort
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{
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public:
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DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
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: CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
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{ }
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virtual void setPeer(Port *port);
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protected:
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virtual bool recvTiming(PacketPtr pkt);
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virtual void recvRetry();
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struct DTickEvent : public TickEvent
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{
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DTickEvent(TimingSimpleCPU *_cpu)
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: TickEvent(_cpu) {}
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void process();
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const char *description() const { return "Timing CPU dcache tick"; }
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};
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DTickEvent tickEvent;
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};
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IcachePort icachePort;
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DcachePort dcachePort;
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PacketPtr ifetch_pkt;
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PacketPtr dcache_pkt;
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Tick previousTick;
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public:
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virtual Port *getPort(const std::string &if_name, int idx = -1);
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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virtual unsigned int drain(Event *drain_event);
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virtual void resume();
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void switchOut();
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void takeOverFrom(BaseCPU *oldCPU);
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
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Fault writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res);
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void fetch();
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void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
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void completeIfetch(PacketPtr );
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void completeDataAccess(PacketPtr pkt);
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void advanceInst(Fault fault);
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/**
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* Print state of address in memory system via PrintReq (for
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* debugging).
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*/
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void printAddr(Addr a);
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/**
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* Finish a DTB translation.
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* @param state The DTB translation state.
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*/
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void finishTranslation(WholeTranslationState *state);
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private:
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typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
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FetchEvent fetchEvent;
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struct IprEvent : Event {
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Packet *pkt;
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TimingSimpleCPU *cpu;
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IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
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virtual void process();
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virtual const char *description() const;
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};
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void completeDrain();
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};
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#endif // __CPU_SIMPLE_TIMING_HH__
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