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Gabe Black 3989f41261 O3: When waiting to handle an interrupt, let everything drain out. 
Before this change, the commit stage would wait until the ROB and store queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then wait
until a valid time to interrupt the instruction stream. Instructions might be
in flight after fetch but not the in the ROB or store queue (in rename, for
instance), so this change makes commit wait until all in flight instructions
are finished.
2011-08-09 03:37:43 -07:00
build_opts Scons: Drop RUBY as compile time option. 2011-08-02 00:10:08 -05:00
configs Scons: Drop RUBY as compile time option. 2011-08-02 00:10:08 -05:00
ext LibElf: Build the error management code in libelf. 2011-06-12 23:51:59 -07:00
src O3: When waiting to handle an interrupt, let everything drain out. 2011-08-09 03:37:43 -07:00
system ARM: Boot loader changes that make it more flexible about load and I/O addrs 2011-05-04 20:38:27 -05:00
tests BuildEnv: Eliminate RUBY as build environment variable 2011-08-08 10:50:13 -05:00
util O3: Create a pipeline activity viewer for the O3 CPU model. 2011-07-15 11:53:35 -05:00
.hgignore .hgignore: added src/doxygen 2010-07-27 20:00:38 -07:00
.hgtags Added tag Calvin_Submission for changeset 5de565c4b7bd 2009-11-18 11:55:42 -06:00
COPYING copyright: Add code for finding all copyright blocks and create a COPYING file 2011-06-02 17:36:07 -07:00
LICENSE copyright: Add code for finding all copyright blocks and create a COPYING file 2011-06-02 17:36:07 -07:00
README Info: Clean up some info files. 2011-02-14 21:36:37 -08:00
SConstruct BuildEnv: Eliminate RUBY as build environment variable 2011-08-08 10:50:13 -05:00

README 

This is the M5 simulator.

For detailed information about building the simulator and getting
started please refer to http://www.m5sim.org.

Specific pages of interest are:
http://www.m5sim.org/wiki/index.php/Compiling_M5
http://www.m5sim.org/wiki/index.php/Running_M5

Short version:

1. If you don't have SCons version 0.98.1 or newer, get it from
http://wwww.scons.org.

2. If you don't have SWIG version 1.3.31 or newer, get it from
http://wwww.swig.org.

3. Make sure you also have gcc version 3.4.6 or newer, Python 2.4 or newer
(the dev version with header files), zlib, and the m4 preprocessor.

4. In this directory, type 'scons build/ALPHA_SE/tests/debug/quick'.  This
will build the debug version of the m5 binary (m5.debug) for the Alpha
syscall emulation target, and run the quick regression tests on it.

If you have questions, please send mail to m5-users@m5sim.org

WHAT'S INCLUDED (AND NOT)
-------------------------

The basic source release includes these subdirectories:
 - m5:
   - configs: simulation configuration scripts
   - ext: less-common external packages needed to build m5
   - src: source code of the m5 simulator
   - system: source for some optional system software for simulated systems
   - tests: regression tests
   - util: useful utility programs and files

To run full-system simulations, you will need compiled system firmware
(console and PALcode for Alpha), kernel binaries and one or more disk images. 
These files for Alpha are collected in a separate archive, m5_system.tar.bz2.
This file can he downloaded separately.

Depending on the ISA used, M5 may support Linux 2.4/2.6, FreeBSD, and the
proprietary Compaq/HP Tru64 version of Unix. We are able to distribute Linux
and FreeBSD bootdisks, but we are unable to distribute bootable disk images of
Tru64 Unix. If you have a Tru64 license and are interested in
obtaining disk images, contact us at m5-users@m5sim.org