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gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt
Andreas Sandberg 55ed9609f1 stats: Update to match classic memory changes
2016-08-12 14:12:59 +01:00

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---------- Begin Simulation Statistics ----------
sim_seconds 47.383918 # Number of seconds simulated
sim_ticks 47383917710000 # Number of ticks simulated
final_tick 47383917710000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 126839 # Simulator instruction rate (inst/s)
host_op_rate 149150 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 6559041658 # Simulator tick rate (ticks/s)
host_mem_usage 782584 # Number of bytes of host memory used
host_seconds 7224.21 # Real time elapsed on the host
sim_insts 916315151 # Number of instructions simulated
sim_ops 1077489368 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker 217728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 211200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 4242016 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 16335944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher 21100544 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 95616 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 61568 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 3171760 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 9979472 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher 12170752 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 426688 # Number of bytes read from this memory
system.physmem.bytes_read::total 68013288 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 4242016 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 3171760 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 7413776 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 84160640 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
system.physmem.bytes_written::total 84181224 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 3402 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 3300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 82234 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 255262 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher 329696 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1494 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 962 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 49603 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 155942 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher 190168 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 6667 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1078730 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1315010 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1317584 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 4595 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 4457 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 89524 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 344757 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher 445310 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 2018 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 1299 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 66937 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 210609 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher 256854 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 9005 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1435366 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 89524 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 66937 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 156462 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1776144 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1776578 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1776144 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 4595 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 4457 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 89524 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 345191 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher 445310 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 2018 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 1299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 66937 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 210609 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher 256854 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 9005 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3211944 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1078730 # Number of read requests accepted
system.physmem.writeReqs 1317584 # Number of write requests accepted
system.physmem.readBursts 1078730 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1317584 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 69010688 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 28032 # Total number of bytes read from write queue
system.physmem.bytesWritten 84179968 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 68013288 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 84181224 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 438 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 67696 # Per bank write bursts
system.physmem.perBankRdBursts::1 73149 # Per bank write bursts
system.physmem.perBankRdBursts::2 67549 # Per bank write bursts
system.physmem.perBankRdBursts::3 71981 # Per bank write bursts
system.physmem.perBankRdBursts::4 66956 # Per bank write bursts
system.physmem.perBankRdBursts::5 73789 # Per bank write bursts
system.physmem.perBankRdBursts::6 64889 # Per bank write bursts
system.physmem.perBankRdBursts::7 66635 # Per bank write bursts
system.physmem.perBankRdBursts::8 57075 # Per bank write bursts
system.physmem.perBankRdBursts::9 82656 # Per bank write bursts
system.physmem.perBankRdBursts::10 58467 # Per bank write bursts
system.physmem.perBankRdBursts::11 69413 # Per bank write bursts
system.physmem.perBankRdBursts::12 60741 # Per bank write bursts
system.physmem.perBankRdBursts::13 63810 # Per bank write bursts
system.physmem.perBankRdBursts::14 67156 # Per bank write bursts
system.physmem.perBankRdBursts::15 66330 # Per bank write bursts
system.physmem.perBankWrBursts::0 82175 # Per bank write bursts
system.physmem.perBankWrBursts::1 87404 # Per bank write bursts
system.physmem.perBankWrBursts::2 82364 # Per bank write bursts
system.physmem.perBankWrBursts::3 86039 # Per bank write bursts
system.physmem.perBankWrBursts::4 82832 # Per bank write bursts
system.physmem.perBankWrBursts::5 88693 # Per bank write bursts
system.physmem.perBankWrBursts::6 80795 # Per bank write bursts
system.physmem.perBankWrBursts::7 83065 # Per bank write bursts
system.physmem.perBankWrBursts::8 76149 # Per bank write bursts
system.physmem.perBankWrBursts::9 79916 # Per bank write bursts
system.physmem.perBankWrBursts::10 77037 # Per bank write bursts
system.physmem.perBankWrBursts::11 82986 # Per bank write bursts
system.physmem.perBankWrBursts::12 77147 # Per bank write bursts
system.physmem.perBankWrBursts::13 80171 # Per bank write bursts
system.physmem.perBankWrBursts::14 84038 # Per bank write bursts
system.physmem.perBankWrBursts::15 84501 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 50212 # Number of times write queue was full causing retry
system.physmem.totGap 47383916196500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 21334 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1057371 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1315010 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 477824 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 264556 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 85571 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 63109 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 41587 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 35911 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 32865 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 30424 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 27932 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 7543 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 3912 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 2354 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 1437 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 1085 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 609 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 513 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 445 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 357 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 146 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 93 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 22527 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 26520 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 36837 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 42274 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 46464 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 50322 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 56496 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 61138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 66561 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 68608 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 74012 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 78194 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 76215 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 79218 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 90231 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 80845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 75138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 70175 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 5598 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 3927 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 2866 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 2290 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 1845 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 1544 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 1368 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1258 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 1266 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 1360 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 1411 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 1419 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 1282 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 1482 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 1488 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 1820 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 1958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 2035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 2146 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 2370 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 2522 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 2687 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 2917 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 2998 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 2934 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 3116 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 3382 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 4014 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 5428 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 24238 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 118579 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1002120 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 152.866515 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 102.517170 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 198.697434 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 641919 64.06% 64.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 209293 20.89% 84.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 56817 5.67% 90.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 24891 2.48% 93.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 19538 1.95% 95.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 11144 1.11% 96.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7510 0.75% 96.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 6154 0.61% 97.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 24854 2.48% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1002120 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 61846 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 17.434870 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 71.484606 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511 61843 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 61846 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 61846 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 21.267535 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.561626 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 606.950117 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-4095 61844 100.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 61846 # Writes before turning the bus around for reads
system.physmem.totQLat 51075620081 # Total ticks spent queuing
system.physmem.totMemAccLat 71293595081 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 5391460000 # Total ticks spent in databus transfers
system.physmem.avgQLat 47367.15 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 66117.15 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.78 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.44 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
system.physmem.avgWrQLen 23.55 # Average write queue length when enqueuing
system.physmem.readRowHits 810741 # Number of row buffer hits during reads
system.physmem.writeRowHits 580742 # Number of row buffer hits during writes
system.physmem.readRowHitRate 75.19 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 44.15 # Row buffer hit rate for writes
system.physmem.avgGap 19773667.47 # Average gap between requests
system.physmem.pageHitRate 58.13 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 3929423400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 2144030625 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 4310615400 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 4363418160 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy 1164748800645 # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy 27408641092500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 31683024522570 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.645104 # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE 45596671664426 # Time in different power states
system.physmem_0.memoryStateTime::REF 1582253140000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 204992820574 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 3646603800 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 1989714375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 4100054400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 4159803600 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 3094887141840 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 1159320938310 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 27413402375250 # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy 31681506631575 # Total energy per rank (pJ)
system.physmem_1.averagePower 668.613070 # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE 45604605403923 # Time in different power states
system.physmem_1.memoryStateTime::REF 1582253140000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 197059081077 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
system.cpu0.branchPred.lookups 139955722 # Number of BP lookups
system.cpu0.branchPred.condPredicted 92576910 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 6767718 # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups 98409045 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 61922323 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 62.923406 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 19026711 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 185987 # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups 4326684 # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits 2749366 # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses 1577318 # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted 397214 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks 611788 # Table walker walks requested
system.cpu0.dtb.walker.walksLong 611788 # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13108 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 98298 # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore 292807 # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples 318981 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean 2428.828049 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 13543.109769 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535 316274 99.15% 99.15% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071 2036 0.64% 99.79% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607 442 0.14% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143 138 0.04% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679 53 0.02% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total 318981 # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples 326187 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 22022.583671 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18838.451550 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 17664.426007 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535 321608 98.60% 98.60% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3320 1.02% 99.61% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607 429 0.13% 99.75% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143 611 0.19% 99.93% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679 146 0.04% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215 45 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total 326187 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 530119453936 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean 0.586335 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev 0.554664 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 528635854936 99.72% 99.72% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3 807711000 0.15% 99.87% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5 321496500 0.06% 99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7 138249500 0.03% 99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9 109943500 0.02% 99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11 58618500 0.01% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13 20610000 0.00% 99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15 26013000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17 940000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19 17000 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 530119453936 # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K 98298 88.23% 88.23% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M 13108 11.77% 100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total 111406 # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 611788 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 611788 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111406 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111406 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total 723194 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 102674478 # DTB read hits
system.cpu0.dtb.read_misses 445170 # DTB read misses
system.cpu0.dtb.write_hits 82832935 # DTB write hits
system.cpu0.dtb.write_misses 166618 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 42795 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 479 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 7037 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 40072 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 103119648 # DTB read accesses
system.cpu0.dtb.write_accesses 82999553 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 185507413 # DTB hits
system.cpu0.dtb.misses 611788 # DTB misses
system.cpu0.dtb.accesses 186119201 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks 85546 # Table walker walks requested
system.cpu0.itb.walker.walksLong 85546 # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1054 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59782 # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore 10366 # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples 75180 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean 1322.160149 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 9414.531253 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-32767 74314 98.85% 98.85% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.60% 99.44% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-98303 228 0.30% 99.75% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::98304-131071 153 0.20% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 75180 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 71202 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 26797.709334 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23346.070270 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 22372.473032 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535 68772 96.59% 96.59% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071 2000 2.81% 99.40% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607 197 0.28% 99.67% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143 144 0.20% 99.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.95% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 71202 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 422744199036 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean 0.876427 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev 0.329334 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 52271860780 12.36% 12.36% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1 370441299256 87.63% 99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2 29828500 0.01% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3 1210500 0.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 422744199036 # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K 59782 98.27% 98.27% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M 1054 1.73% 100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total 60836 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85546 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85546 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60836 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60836 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 146382 # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits 220474674 # ITB inst hits
system.cpu0.itb.inst_misses 85546 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 31037 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 205838 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 220560220 # ITB inst accesses
system.cpu0.itb.hits 220474674 # DTB hits
system.cpu0.itb.misses 85546 # DTB misses
system.cpu0.itb.accesses 220560220 # DTB accesses
system.cpu0.numPwrStateTransitions 10840 # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples 5420 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean 8671662092.472324 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev 149203914828.202179 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows 3833 70.72% 70.72% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10 1557 28.73% 99.45% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11 11 0.20% 99.65% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 3 0.06% 99.70% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows 13 0.24% 100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 6993554617000 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total 5420 # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON 383509168800 # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 47000408541200 # Cumulative time (in ticks) in various power states
system.cpu0.numCycles 767019929 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles 88196996 # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts 619911097 # Number of instructions fetch has processed
system.cpu0.fetch.Branches 139955722 # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches 83698400 # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles 636708825 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 14589342 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 2007819 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 289070 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles 6017581 # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles 759490 # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles 830550 # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines 220269194 # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes 1684756 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 27864 # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples 742105002 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean 0.977120 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev 1.219124 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0 394679215 53.18% 53.18% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1 135211877 18.22% 71.40% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2 46727804 6.30% 77.70% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3 165486106 22.30% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total 742105002 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.182467 # Number of branch fetches per cycle
system.cpu0.fetch.rate 0.808207 # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles 106471358 # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles 362106065 # Number of cycles decode is blocked
system.cpu0.decode.RunCycles 229306920 # Number of cycles decode is running
system.cpu0.decode.UnblockCycles 38969186 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 5251473 # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved 19951761 # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred 2082457 # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts 641630797 # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts 23347252 # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles 5251473 # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles 142650653 # Number of cycles rename is idle
system.cpu0.rename.BlockCycles 53065481 # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles 241402745 # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles 231558396 # Number of cycles rename is running
system.cpu0.rename.UnblockCycles 68176254 # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts 624076980 # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts 6229632 # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents 10704846 # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents 385160 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 931811 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 31501280 # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents 11804 # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands 596222700 # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups 963956032 # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups 736577059 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 695179 # Number of floating rename lookups
system.cpu0.rename.CommittedMaps 537389975 # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps 58832686 # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts 16140854 # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts 14103711 # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts 78118251 # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads 102816112 # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores 86124751 # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads 9533509 # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores 8142362 # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded 600960924 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 16329392 # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued 605893488 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 2751703 # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined 55206879 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined 35882934 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 285911 # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples 742105002 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean 0.816453 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev 1.065729 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0 411055814 55.39% 55.39% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1 139198751 18.76% 74.15% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2 116841261 15.74% 89.89% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3 67029634 9.03% 98.92% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4 7974397 1.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5 5145 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total 742105002 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu 62807824 45.43% 45.43% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult 65216 0.05% 45.48% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv 15839 0.01% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc 32 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.49% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead 36880846 26.68% 72.17% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 38467267 27.83% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 25 0.00% 0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu 414236377 68.37% 68.37% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult 1540158 0.25% 68.62% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 80647 0.01% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 9 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp 1 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc 41778 0.01% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead 105913797 17.48% 86.12% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite 84080696 13.88% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total 605893488 # Type of FU issued
system.cpu0.iq.rate 0.789932 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 138237024 # FU busy when requested
system.cpu0.iq.fu_busy_rate 0.228154 # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads 2093764115 # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes 672208466 # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses 588253598 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 1116590 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 439713 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 411739 # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses 743434871 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 695616 # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads 2774549 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads 12838296 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 17783 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 152412 # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores 5562268 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 2788433 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 4754457 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 5251473 # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles 7932610 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 1687524 # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts 617423509 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts 102816112 # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts 86124751 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 13854081 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 62183 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 1552208 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 152412 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 1974984 # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect 3105212 # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts 5080196 # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts 597824194 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 102668745 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 7465093 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
system.cpu0.iew.exec_nop 133193 # number of nop insts executed
system.cpu0.iew.exec_refs 185500111 # number of memory reference insts executed
system.cpu0.iew.exec_branches 112433305 # Number of branches executed
system.cpu0.iew.exec_stores 82831366 # Number of stores executed
system.cpu0.iew.exec_rate 0.779412 # Inst execution rate
system.cpu0.iew.wb_sent 589443856 # cumulative count of insts sent to commit
system.cpu0.iew.wb_count 588665337 # cumulative count of insts written-back
system.cpu0.iew.wb_producers 287005457 # num instructions producing a value
system.cpu0.iew.wb_consumers 470602155 # num instructions consuming a value
system.cpu0.iew.wb_rate 0.767471 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.609869 # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts 48230515 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 16043481 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 4724520 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples 732949405 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean 0.766879 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev 1.569816 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0 487135616 66.46% 66.46% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1 127506386 17.40% 83.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2 54345658 7.41% 91.27% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3 18167389 2.48% 93.75% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4 13030534 1.78% 95.53% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5 9013680 1.23% 96.76% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6 6080548 0.83% 97.59% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7 3647046 0.50% 98.09% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 14022548 1.91% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 732949405 # Number of insts commited each cycle
system.cpu0.commit.committedInsts 479057822 # Number of instructions committed
system.cpu0.commit.committedOps 562083399 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 170540284 # Number of memory references committed
system.cpu0.commit.loads 89977801 # Number of loads committed
system.cpu0.commit.membars 3918882 # Number of memory barriers committed
system.cpu0.commit.branches 106864519 # Number of branches committed
system.cpu0.commit.fp_insts 404083 # Number of committed floating point instructions.
system.cpu0.commit.int_insts 515735338 # Number of committed integer instructions.
system.cpu0.commit.function_calls 14196925 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu 390151246 69.41% 69.41% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 1292004 0.23% 69.64% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 63609 0.01% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.65% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc 36256 0.01% 69.66% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.66% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.66% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.66% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead 89977801 16.01% 85.67% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite 80562483 14.33% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total 562083399 # Class of committed instruction
system.cpu0.commit.bw_lim_events 14022548 # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads 1325013729 # The number of ROB reads
system.cpu0.rob.rob_writes 1229746140 # The number of ROB writes
system.cpu0.timesIdled 998783 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 24914927 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 94000815527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 479057822 # Number of Instructions Simulated
system.cpu0.committedOps 562083399 # Number of Ops (including micro ops) Simulated
system.cpu0.cpi 1.601101 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 1.601101 # CPI: Total CPI of All Threads
system.cpu0.ipc 0.624570 # IPC: Instructions Per Cycle
system.cpu0.ipc_total 0.624570 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 705670279 # number of integer regfile reads
system.cpu0.int_regfile_writes 419695299 # number of integer regfile writes
system.cpu0.fp_regfile_reads 680997 # number of floating regfile reads
system.cpu0.fp_regfile_writes 310212 # number of floating regfile writes
system.cpu0.cc_regfile_reads 130338984 # number of cc regfile reads
system.cpu0.cc_regfile_writes 131056521 # number of cc regfile writes
system.cpu0.misc_regfile_reads 1328403158 # number of misc regfile reads
system.cpu0.misc_regfile_writes 16107336 # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 6279329 # number of replacements
system.cpu0.dcache.tags.tagsinuse 481.718631 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 157880144 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 6279840 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 25.140791 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 1908955000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.718631 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940857 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.940857 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 218 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 354237308 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 354237308 # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data 83229187 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 83229187 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 69700757 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 69700757 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201759 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 201759 # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data 148045 # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total 148045 # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1863463 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 1863463 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1922512 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 1922512 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 153077989 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 153077989 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 153279748 # number of overall hits
system.cpu0.dcache.overall_hits::total 153279748 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 7047364 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 7047364 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 7798246 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 7798246 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 750513 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 750513 # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796040 # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total 796040 # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 285990 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 285990 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189707 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 189707 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 15641650 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 15641650 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 16392163 # number of overall misses
system.cpu0.dcache.overall_misses::total 16392163 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 106587069500 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 106587069500 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 149276619912 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 149276619912 # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30060531759 # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total 30060531759 # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4170219500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 4170219500 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536657500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 4536657500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2221500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2221500 # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 285924221171 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 285924221171 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 285924221171 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 285924221171 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 90276551 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 90276551 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 77499003 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 77499003 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 952272 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 952272 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 944085 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total 944085 # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2149453 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 2149453 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2112219 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 2112219 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 168719639 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 168719639 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 169671911 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 169671911 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.078064 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.078064 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100624 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.100624 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.788129 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788129 # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.843187 # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total 0.843187 # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.133052 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.133052 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089814 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089814 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092708 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.092708 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096611 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.096611 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15124.388282 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 15124.388282 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19142.332765 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 19142.332765 # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37762.589517 # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37762.589517 # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14581.696912 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14581.696912 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23914.022677 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23914.022677 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18279.671337 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 18279.671337 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17442.739019 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 17442.739019 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 9136124 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 22955799 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 744485 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 773832 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.271737 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 29.665094 # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 6279393 # number of writebacks
system.cpu0.dcache.writebacks::total 6279393 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3627313 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 3627313 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6268862 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 6268862 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4039 # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total 4039 # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 145852 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 145852 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data 9900214 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 9900214 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data 9900214 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 9900214 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3420051 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 3420051 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1529384 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 1529384 # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 743716 # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total 743716 # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792001 # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total 792001 # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140138 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140138 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189707 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 189707 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data 5741436 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 5741436 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 6485152 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 6485152 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17085 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17085 # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18834 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18834 # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35919 # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35919 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49260241500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 49260241500 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 32250000948 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 32250000948 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16897998500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16897998500 # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29124405259 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29124405259 # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1866604500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1866604500 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4347004500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4347004500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2167500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2167500 # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 110634647707 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 110634647707 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 127532646207 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 127532646207 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3215151000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3215151000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3215151000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3215151000 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037884 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037884 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019734 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019734 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.780991 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.780991 # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.838909 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.838909 # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065197 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065197 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089814 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089814 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034029 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.034029 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038222 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.038222 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14403.364599 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14403.364599 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21086.921890 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21086.921890 # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22721.036659 # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22721.036659 # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36773.192533 # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36773.192533 # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13319.759808 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13319.759808 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22914.307327 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22914.307327 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19269.508135 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19269.508135 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19665.328771 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19665.328771 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 188185.601405 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188185.601405 # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89511.150088 # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89511.150088 # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 5960489 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.962298 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 213927686 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 5961001 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 35.887880 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 13033031000 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.962298 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999926 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999926 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 342 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 446443685 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 446443685 # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst 213927686 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 213927686 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 213927686 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 213927686 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 213927686 # number of overall hits
system.cpu0.icache.overall_hits::total 213927686 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 6313628 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 6313628 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 6313628 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 6313628 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 6313628 # number of overall misses
system.cpu0.icache.overall_misses::total 6313628 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 68941695345 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 68941695345 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst 68941695345 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 68941695345 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst 68941695345 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 68941695345 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 220241314 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 220241314 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 220241314 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 220241314 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 220241314 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 220241314 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028667 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.028667 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028667 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.028667 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028667 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.028667 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10919.505448 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 10919.505448 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10919.505448 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 10919.505448 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10919.505448 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 10919.505448 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 10186888 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 465 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 736848 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 9 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.824952 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 51.666667 # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks 5960489 # number of writebacks
system.cpu0.icache.writebacks::total 5960489 # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 352571 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 352571 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst 352571 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 352571 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst 352571 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 352571 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5961057 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 5961057 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst 5961057 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 5961057 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 5961057 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 5961057 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 62354110053 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 62354110053 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 62354110053 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 62354110053 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 62354110053 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 62354110053 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1885677498 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1885677498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 1885677498 # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027066 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.027066 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027066 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.027066 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10460.243888 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10460.243888 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10460.243888 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88558.563753 # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88558.563753 # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88558.563753 # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued 8592940 # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified 8600926 # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit 7220 # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 1116114 # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements 2719287 # number of replacements
system.cpu0.l2cache.tags.tagsinuse 15847.951353 # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs 10783985 # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs 2734787 # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs 3.943263 # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle 2212469000 # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15472.818870 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.262850 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.351912 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 323.517722 # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks 0.944386 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002030 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001120 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019746 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total 0.967282 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022 300 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 95 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 82 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 118 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 22 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 45 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2056 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7291 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3067 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2287 # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018311 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses 426577615 # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses 426577615 # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 609078 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 186922 # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total 796000 # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks 4110828 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total 4110828 # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks 8127250 # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total 8127250 # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 41 # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 5 # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total 5 # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991441 # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total 991441 # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5365262 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total 5365262 # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3250561 # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total 3250561 # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 179546 # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total 179546 # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 609078 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker 186922 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst 5365262 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data 4242002 # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total 10403264 # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 609078 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker 186922 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst 5365262 # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data 4242002 # number of overall hits
system.cpu0.l2cache.overall_hits::total 10403264 # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 23667 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12082 # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total 35749 # number of ReadReq misses
system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses
system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 259915 # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total 259915 # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189699 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total 189699 # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data 286982 # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total 286982 # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 595762 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total 595762 # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1051075 # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total 1051075 # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 610539 # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total 610539 # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 23667 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12082 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst 595762 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data 1338057 # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total 1969568 # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 23667 # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12082 # number of overall misses
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system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4803983000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1725979000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 3078004000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4803983000 # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.042391 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999842 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999842 # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999974 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999974 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209906 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209906 # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.099943 # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243132 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243132 # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772747 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772747 # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total 0.157218 # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.037192 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.058923 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099943 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.235520 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total 0.228959 # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32290.152869 # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59475.138338 # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18533.216598 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18533.216598 # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15397.474383 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15397.474383 # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 587500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 587500 # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 45129.381880 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 45129.381880 # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29103.997241 # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31830.259628 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31830.259628 # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36425.359014 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36425.359014 # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32838.272405 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28922.853015 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 39048.012963 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 29103.997241 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34545.803791 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59475.138338 # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 41184.535280 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180158.267486 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 125175.439054 # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81058.516883 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85692.920182 # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83968.101098 # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests 25397703 # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13066663 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1795 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops 671473 # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 671468 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq 963728 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 11315166 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 18834 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 18834 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty 5872564 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean 8129050 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict 1348327 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq 1122615 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp 22 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq 466810 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 338240 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp 510310 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 1307620 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 1285212 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5961057 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5219350 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq 843100 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp 790085 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 17925156 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20147173 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 419117 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1337980 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total 39829426 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 763317520 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 765224037 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1592032 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5061960 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total 1535195549 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops 5838031 # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic 119621704 # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples 19351504 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean 0.054273 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev 0.226556 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 18301249 94.57% 94.57% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 1050250 5.43% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 5 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total 19351504 # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy 25250991712 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy 173970437 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy 8969219750 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy 9025116687 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 220608496 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy 706093257 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.branchPred.lookups 128968222 # Number of BP lookups
system.cpu1.branchPred.condPredicted 85282466 # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect 6518355 # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups 89675287 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 55364340 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 61.738682 # BTB Hit Percentage
system.cpu1.branchPred.usedRAS 17439644 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 182879 # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups 4134289 # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits 2557852 # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses 1576437 # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted 401535 # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks 531460 # Table walker walks requested
system.cpu1.dtb.walker.walksLong 531460 # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10155 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 82594 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 244261 # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples 287199 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean 2189.199823 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 12408.912934 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-32767 282304 98.30% 98.30% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::32768-65535 2996 1.04% 99.34% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-98303 743 0.26% 99.60% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::98304-131071 602 0.21% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-163839 197 0.07% 99.88% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::163840-196607 152 0.05% 99.93% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-229375 103 0.04% 99.96% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::229376-262143 33 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-294911 16 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::294912-327679 35 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-360447 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total 287199 # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples 267684 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 20635.114538 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18133.747768 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 11911.787641 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-32767 239914 89.63% 89.63% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::32768-65535 26330 9.84% 99.46% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-98303 756 0.28% 99.74% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::98304-131071 476 0.18% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-163839 73 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::163840-196607 24 0.01% 99.96% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-229375 55 0.02% 99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::229376-262143 22 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::294912-327679 8 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::425984-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total 267684 # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 465694213496 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean 0.593113 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev 0.550788 # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 464589649996 99.76% 99.76% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3 559093500 0.12% 99.88% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5 239052500 0.05% 99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7 120378000 0.03% 99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9 87009500 0.02% 99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11 57335500 0.01% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13 14978500 0.00% 99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15 26310000 0.01% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17 396500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19 9500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 465694213496 # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K 82595 89.05% 89.05% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M 10155 10.95% 100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total 92750 # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 531460 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 531460 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 92750 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 92750 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total 624210 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 93944307 # DTB read hits
system.cpu1.dtb.read_misses 364370 # DTB read misses
system.cpu1.dtb.write_hits 78170381 # DTB write hits
system.cpu1.dtb.write_misses 167090 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 34720 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 381 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 5735 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 39000 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 94308677 # DTB read accesses
system.cpu1.dtb.write_accesses 78337471 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 172114688 # DTB hits
system.cpu1.dtb.misses 531460 # DTB misses
system.cpu1.dtb.accesses 172646148 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks 82381 # Table walker walks requested
system.cpu1.itb.walker.walksLong 82381 # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1018 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59631 # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore 9853 # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples 72528 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean 882.590172 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev 6870.472006 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-32767 72114 99.43% 99.43% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::32768-65535 279 0.38% 99.81% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-98303 39 0.05% 99.87% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::98304-131071 75 0.10% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::163840-196607 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 72528 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 70502 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 24022.878784 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22243.496704 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 12757.621468 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-32767 63844 90.56% 90.56% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::32768-65535 6070 8.61% 99.17% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-98303 93 0.13% 99.30% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::98304-131071 382 0.54% 99.84% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-163839 44 0.06% 99.90% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::163840-196607 19 0.03% 99.93% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-229375 18 0.03% 99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::229376-262143 8 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 70502 # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 379792000076 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean 0.874646 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev 0.331269 # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0 47625596788 12.54% 12.54% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1 332150851288 87.46% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2 14331500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3 990000 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4 230500 0.00% 100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 379792000076 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 59631 98.32% 98.32% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M 1018 1.68% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 60649 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82381 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82381 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60649 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60649 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 143030 # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits 201934152 # ITB inst hits
system.cpu1.itb.inst_misses 82381 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 44145 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 1062 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 24569 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 202631 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 202016533 # ITB inst accesses
system.cpu1.itb.hits 201934152 # DTB hits
system.cpu1.itb.misses 82381 # DTB misses
system.cpu1.itb.accesses 202016533 # DTB accesses
system.cpu1.numPwrStateTransitions 26784 # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples 13392 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean 3512583180.059961 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev 88770415671.353104 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows 3351 25.02% 25.02% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10 10014 74.78% 99.80% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.81% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.82% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 4 0.03% 99.85% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::3.5e+11-4e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7430623145540 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total 13392 # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON 343403762637 # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47040513947363 # Cumulative time (in ticks) in various power states
system.cpu1.numCycles 686817572 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles 87491536 # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts 569150585 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 128968222 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 75361836 # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles 564504137 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 14030828 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 1743458 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 273069 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles 5670150 # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles 713565 # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles 783781 # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines 201710843 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 1678338 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 26867 # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples 668195110 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.000138 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 1.225435 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0 348421230 52.14% 52.14% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 124504424 18.63% 70.78% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 42025261 6.29% 77.07% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 153244195 22.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total 668195110 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.187777 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.828678 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 102161242 # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles 311763510 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 215198558 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 34078749 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 4993051 # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved 18208977 # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred 2060516 # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts 590405276 # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts 22672761 # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles 4993051 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 135354794 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 41008219 # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles 216515907 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 215714387 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 54608752 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 573925738 # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts 5865325 # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents 9111156 # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents 235226 # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents 246551 # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents 22706071 # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents 10845 # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands 544713354 # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups 881414288 # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups 677140554 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 799785 # Number of floating rename lookups
system.cpu1.rename.CommittedMaps 489645115 # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps 55068233 # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts 14685141 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 12835902 # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts 68922736 # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads 94552173 # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores 81340147 # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads 8760661 # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores 7542596 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 552653279 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 14818656 # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued 556478216 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 2578197 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 52065959 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 33349277 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 259122 # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples 668195110 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean 0.832808 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.070079 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0 364178661 54.50% 54.50% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1 127786531 19.12% 73.63% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2 107346035 16.07% 89.69% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 61539810 9.21% 98.90% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 7340180 1.10% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 3893 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total 668195110 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 55774345 44.07% 44.07% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 53478 0.04% 44.12% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 18362 0.01% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc 15 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.13% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead 33579431 26.53% 70.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite 37124892 29.34% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 35 0.00% 0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu 378772554 68.07% 68.07% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult 1203453 0.22% 68.28% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv 69506 0.01% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 82169 0.01% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.31% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead 96967073 17.43% 85.73% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 79383378 14.27% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total 556478216 # Type of FU issued
system.cpu1.iq.rate 0.810227 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 126550523 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.227413 # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads 1908944024 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 619142753 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 540109020 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 1336236 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 533681 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 496559 # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses 682200972 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 827732 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 2535076 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads 12050927 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 15964 # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation 139670 # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores 5367770 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 2479862 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 3811174 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 4993051 # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles 6066595 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 1484920 # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts 567600146 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts 94552173 # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts 81340147 # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts 12593166 # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents 61012 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 1366008 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 139670 # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect 1864288 # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect 2962654 # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts 4826942 # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts 548760252 # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts 93936954 # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts 7198002 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 128211 # number of nop insts executed
system.cpu1.iew.exec_refs 172107181 # number of memory reference insts executed
system.cpu1.iew.exec_branches 103045741 # Number of branches executed
system.cpu1.iew.exec_stores 78170227 # Number of stores executed
system.cpu1.iew.exec_rate 0.798990 # Inst execution rate
system.cpu1.iew.wb_sent 541337937 # cumulative count of insts sent to commit
system.cpu1.iew.wb_count 540605579 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 260784878 # num instructions producing a value
system.cpu1.iew.wb_consumers 427489689 # num instructions consuming a value
system.cpu1.iew.wb_rate 0.787117 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.610038 # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts 45375845 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 14559534 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 4495992 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples 659550921 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean 0.781450 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev 1.574730 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0 433210493 65.68% 65.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1 117319741 17.79% 83.47% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 50366969 7.64% 91.11% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 16989740 2.58% 93.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4 12025543 1.82% 95.51% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5 8091474 1.23% 96.73% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6 5593324 0.85% 97.58% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7 3365512 0.51% 98.09% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8 12588125 1.91% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 659550921 # Number of insts commited each cycle
system.cpu1.commit.committedInsts 437257329 # Number of instructions committed
system.cpu1.commit.committedOps 515405969 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 158473622 # Number of memory references committed
system.cpu1.commit.loads 82501245 # Number of loads committed
system.cpu1.commit.membars 3568741 # Number of memory barriers committed
system.cpu1.commit.branches 97797753 # Number of branches committed
system.cpu1.commit.fp_insts 487077 # Number of committed floating point instructions.
system.cpu1.commit.int_insts 473223690 # Number of committed integer instructions.
system.cpu1.commit.function_calls 12865392 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu 355828768 69.04% 69.04% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult 973462 0.19% 69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 55201 0.01% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc 74874 0.01% 69.25% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead 82501245 16.01% 85.26% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite 75972377 14.74% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 515405969 # Class of committed instruction
system.cpu1.commit.bw_lim_events 12588125 # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads 1203797977 # The number of ROB reads
system.cpu1.rob.rob_writes 1130170940 # The number of ROB writes
system.cpu1.timesIdled 922689 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 18622462 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 94081017888 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 437257329 # Number of Instructions Simulated
system.cpu1.committedOps 515405969 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi 1.570740 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.570740 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.636643 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.636643 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 647634757 # number of integer regfile reads
system.cpu1.int_regfile_writes 384292228 # number of integer regfile writes
system.cpu1.fp_regfile_reads 785728 # number of floating regfile reads
system.cpu1.fp_regfile_writes 454696 # number of floating regfile writes
system.cpu1.cc_regfile_reads 117471222 # number of cc regfile reads
system.cpu1.cc_regfile_writes 118161265 # number of cc regfile writes
system.cpu1.misc_regfile_reads 1199366647 # number of misc regfile reads
system.cpu1.misc_regfile_writes 14671382 # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 5153619 # number of replacements
system.cpu1.dcache.tags.tagsinuse 456.044406 # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs 148207895 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 5154131 # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs 28.755166 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 8517415326000 # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.044406 # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890712 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total 0.890712 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses 328622817 # Number of tag accesses
system.cpu1.dcache.tags.data_accesses 328622817 # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data 76967758 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 76967758 # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data 66682281 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 66682281 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 189501 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 189501 # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data 166829 # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total 166829 # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1726427 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 1726427 # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1743769 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 1743769 # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data 143816868 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 143816868 # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data 144006369 # number of overall hits
system.cpu1.dcache.overall_hits::total 144006369 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 5978399 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 5978399 # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data 6727643 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 6727643 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 625948 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 625948 # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data 458256 # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total 458256 # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 242959 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 242959 # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 183921 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 183921 # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data 13164298 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 13164298 # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data 13790246 # number of overall misses
system.cpu1.dcache.overall_misses::total 13790246 # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87383841500 # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total 87383841500 # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 119886339095 # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 119886339095 # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11324190656 # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total 11324190656 # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3328957500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total 3328957500 # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4379371000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total 4379371000 # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2907500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2907500 # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 218594371251 # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 218594371251 # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 218594371251 # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 218594371251 # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data 82946157 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 82946157 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 73409924 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 73409924 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 815449 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total 815449 # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625085 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total 625085 # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1969386 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 1969386 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1927690 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 1927690 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data 156981166 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 156981166 # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data 157796615 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 157796615 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072076 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.072076 # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.091645 # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total 0.091645 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.767611 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.767611 # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.733110 # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total 0.733110 # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.123368 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.123368 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095410 # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095410 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083859 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.083859 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087393 # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total 0.087393 # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14616.595764 # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 14616.595764 # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17819.961478 # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 17819.961478 # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 24711.494571 # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 24711.494571 # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13701.725394 # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13701.725394 # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23811.152614 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23811.152614 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16605.091381 # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 16605.091381 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15851.375766 # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 15851.375766 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 2917967 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 18895353 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 374678 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 668758 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.787933 # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 28.254395 # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks 5153631 # number of writebacks
system.cpu1.dcache.writebacks::total 5153631 # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3023211 # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total 3023211 # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5427179 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total 5427179 # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3743 # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total 3743 # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127495 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127495 # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data 8454133 # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total 8454133 # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data 8454133 # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total 8454133 # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2955188 # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total 2955188 # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1300464 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 1300464 # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 625861 # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total 625861 # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 454513 # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total 454513 # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 115464 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 115464 # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 183920 # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total 183920 # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data 4710165 # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total 4710165 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 5336026 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 5336026 # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21232 # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40642 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40128990000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40128990000 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24368462066 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24368462066 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13718666000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13718666000 # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10741056156 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10741056156 # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1514532000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1514532000 # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4195522000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4195522000 # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2836500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2836500 # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 75238508222 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total 75238508222 # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 88957174222 # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total 88957174222 # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3718611500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3718611500 # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3718611500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3718611500 # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035628 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035628 # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.017715 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.017715 # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.767505 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.767505 # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.727122 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.727122 # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058629 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058629 # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095410 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095410 # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total 0.030005 # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033816 # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total 0.033816 # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13579.166537 # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13579.166537 # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18738.282694 # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18738.282694 # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21919.669064 # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21919.669064 # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23632.010869 # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23632.010869 # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13116.919559 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13116.919559 # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22811.668117 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22811.668117 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15973.645981 # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15973.645981 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16671.053369 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16671.053369 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 175141.837792 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 175141.837792 # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91496.764431 # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91496.764431 # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements 6014648 # number of replacements
system.cpu1.icache.tags.tagsinuse 501.532915 # Cycle average of tags in use
system.cpu1.icache.tags.total_refs 195349774 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 6015160 # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs 32.476239 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8517720712000 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.532915 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979556 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.979556 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 341 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses 409423979 # Number of tag accesses
system.cpu1.icache.tags.data_accesses 409423979 # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst 195349774 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 195349774 # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst 195349774 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 195349774 # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst 195349774 # number of overall hits
system.cpu1.icache.overall_hits::total 195349774 # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst 6354622 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 6354622 # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst 6354622 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 6354622 # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst 6354622 # number of overall misses
system.cpu1.icache.overall_misses::total 6354622 # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 66668444908 # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total 66668444908 # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst 66668444908 # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total 66668444908 # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst 66668444908 # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total 66668444908 # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst 201704396 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 201704396 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst 201704396 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 201704396 # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst 201704396 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 201704396 # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031505 # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total 0.031505 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031505 # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total 0.031505 # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031505 # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total 0.031505 # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10491.331335 # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10491.331335 # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10491.331335 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10491.331335 # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10491.331335 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 9555681 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 472 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 727552 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.134018 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets 118 # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks 6014648 # number of writebacks
system.cpu1.icache.writebacks::total 6014648 # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 339435 # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total 339435 # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst 339435 # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total 339435 # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst 339435 # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total 339435 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6015187 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 6015187 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 6015187 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 6015187 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 6015187 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 6015187 # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total 68 # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total 68 # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 60428904539 # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total 60428904539 # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 60428904539 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total 60428904539 # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 60428904539 # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total 60428904539 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6183499 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6183499 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6183499 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 6183499 # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.029822 # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total 0.029822 # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.029822 # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total 0.029822 # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10046.055848 # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10046.055848 # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10046.055848 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90933.808824 # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90933.808824 # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90933.808824 # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued 6826847 # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified 6833838 # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit 6347 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 835722 # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements 1955228 # number of replacements
system.cpu1.l2cache.tags.tagsinuse 12896.405710 # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs 10261646 # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs 1970971 # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs 5.206391 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.365224 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 35.187602 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.957161 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 235.895723 # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks 0.768943 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002148 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001645 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.014398 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total 0.787134 # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022 398 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023 66 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15279 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 9 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 92 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 100 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 49 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2171 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6847 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4119 # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1911 # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.024292 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004028 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.932556 # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses 388828691 # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses 388828691 # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 536780 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 184573 # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total 721353 # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks 3280399 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total 3280399 # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks 7886275 # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total 7886275 # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 44 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 44 # number of UpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data 841994 # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total 841994 # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5485264 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total 5485264 # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2792582 # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total 2792582 # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 201829 # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total 201829 # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 536780 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker 184573 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst 5485264 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data 3634576 # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total 9841193 # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 536780 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker 184573 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst 5485264 # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data 3634576 # number of overall hits
system.cpu1.l2cache.overall_hits::total 9841193 # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18586 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8726 # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total 27312 # number of ReadReq misses
system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses
system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 218938 # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total 218938 # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 183916 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total 183916 # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data 248462 # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total 248462 # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 529890 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total 529890 # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 900142 # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total 900142 # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 250350 # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total 250350 # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18586 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8726 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst 529890 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data 1148604 # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total 1705806 # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18586 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8726 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst 529890 # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data 1148604 # number of overall misses
system.cpu1.l2cache.overall_misses::total 1705806 # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 561198500 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 279280000 # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total 840478500 # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 939555000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total 939555000 # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 281624500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 281624500 # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2725499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2725499 # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10972899994 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total 10972899994 # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 18159407000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total 18159407000 # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 31177890486 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total 31177890486 # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 362314500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total 362314500 # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 561198500 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 279280000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst 18159407000 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data 42150790480 # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total 61150675980 # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 561198500 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 279280000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst 18159407000 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data 42150790480 # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total 61150675980 # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 555366 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 193299 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total 748665 # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3280399 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total 3280399 # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks 7886276 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total 7886276 # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 218982 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total 218982 # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 183916 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total 183916 # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1090456 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total 1090456 # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6015154 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total 6015154 # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3692724 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total 3692724 # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 452179 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total 452179 # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 555366 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 193299 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst 6015154 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data 4783180 # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total 11546999 # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 555366 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 193299 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst 6015154 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data 4783180 # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total 11546999 # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.033466 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.045142 # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total 0.036481 # miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999799 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999799 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.227851 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total 0.227851 # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.088093 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.088093 # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.243761 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.243761 # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.553652 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.553652 # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.033466 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.045142 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.088093 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.240134 # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total 0.147727 # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.033466 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.045142 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.088093 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.240134 # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total 0.147727 # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 30194.689551 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 32005.500802 # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30773.231547 # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4291.420402 # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4291.420402 # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1531.266991 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1531.266991 # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 681374.750000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 681374.750000 # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 44163.292552 # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 44163.292552 # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 34270.144747 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 34270.144747 # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 34636.635649 # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 34636.635649 # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1447.231875 # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1447.231875 # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 30194.689551 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 32005.500802 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34270.144747 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 36697.408750 # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 35848.552520 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 30194.689551 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 32005.500802 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34270.144747 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 36697.408750 # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 35848.552520 # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs 288 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 57.600000 # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches 40502 # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks 1084478 # number of writebacks
system.cpu1.l2cache.writebacks::total 1084478 # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 75 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 191 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 10775 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total 10775 # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 2 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4833 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4833 # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 2 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total 2 # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 75 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 191 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data 15608 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total 15876 # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 75 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 191 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data 15608 # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total 15876 # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 18511 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8535 # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total 27046 # number of ReadReq MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses
system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 693628 # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total 693628 # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 218938 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total 218938 # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 183916 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 183916 # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237687 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total 237687 # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 529888 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 529888 # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 895309 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 895309 # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 250348 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total 250348 # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18511 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8535 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 529888 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1132996 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total 1689930 # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18511 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8535 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 529888 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1132996 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 693628 # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total 2383558 # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 68 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21232 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21300 # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 68 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40642 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40710 # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 448702000 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224952500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 673654500 # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 32672970024 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 32672970024 # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4113980492 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4113980492 # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2813333996 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2813333996 # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2299499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2299499 # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7950875496 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7950875496 # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14980050000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14980050000 # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 25503490486 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 25503490486 # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6724179499 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6724179499 # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 448702000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224952500 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14980050000 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 33454365982 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total 49108070482 # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 448702000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224952500 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14980050000 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 33454365982 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 32672970024 # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total 81781040506 # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5673000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3548566000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3554239000 # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5673000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3548566000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3554239000 # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.036126 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999799 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999799 # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.217970 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.217970 # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.088092 # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.242452 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.242452 # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.553648 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.553648 # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146352 # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033331 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044154 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088092 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.236871 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total 0.206422 # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24907.731273 # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 47104.456602 # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18790.618769 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18790.618769 # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15296.842015 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15296.842015 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 574874.750000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 574874.750000 # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33451.032223 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33451.032223 # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 28270.219367 # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 28485.685373 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28485.685373 # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26859.329809 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26859.329809 # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29059.233508 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24239.749338 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 26356.473345 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28270.219367 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29527.346947 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 47104.456602 # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34310.488986 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 167132.912585 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166865.680751 # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83426.470588 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87312.779883 # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87306.288381 # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests 23161545 # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11911126 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1586 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops 559932 # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 559928 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq 858463 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 10650090 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty 4372034 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean 7887876 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict 1202832 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq 877539 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 29 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq 412195 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 333118 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp 458356 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 1116808 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 1095312 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6015187 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4685876 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq 509592 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp 452179 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18045125 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16655613 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 406321 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1179507 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total 36286566 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 769908416 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 641765745 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1546392 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4442928 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total 1417663481 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops 4824103 # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic 76247568 # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples 17122714 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean 0.052642 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev 0.223318 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 16221347 94.74% 94.74% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 901363 5.26% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total 17122714 # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy 23027796506 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy 160947650 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy 9028759604 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy 7641863842 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 213393747 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy 624968323 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq 40315 # Transaction distribution
system.iobus.trans_dist::ReadResp 40315 # Transaction distribution
system.iobus.trans_dist::WriteReq 136630 # Transaction distribution
system.iobus.trans_dist::WriteResp 136630 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47698 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122580 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231230 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231230 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 353890 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47718 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155710 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338936 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7338936 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 7496732 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 36996503 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 24232502 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 36410001 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 568919799 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 92681000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 147926000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements 115610 # number of replacements
system.iocache.tags.tagsinuse 11.211324 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 115626 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 9155814843000 # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet 7.413268 # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide 3.798056 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet 0.463329 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide 0.237379 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.700708 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1040892 # Number of tag accesses
system.iocache.tags.data_accesses 1040892 # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide 8887 # number of ReadReq misses
system.iocache.ReadReq_misses::total 8924 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide 115615 # number of demand (read+write) misses
system.iocache.demand_misses::total 115655 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 115615 # number of overall misses
system.iocache.overall_misses::total 115655 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide 1677259553 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 1682459553 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide 12947566246 # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total 12947566246 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide 14624825799 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 14630394799 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide 14624825799 # number of overall miss cycles
system.iocache.overall_miss_latency::total 14630394799 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8887 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8924 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide 115615 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 115655 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide 115615 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 115655 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 188731.805221 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 188531.998319 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121313.678191 # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 121313.678191 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 126500.322502 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 126495.920071 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 126500.322502 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 33395 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs 9.557813 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.writebacks::writebacks 106693 # number of writebacks
system.iocache.writebacks::total 106693 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8887 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8924 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide 115615 # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total 115655 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 115615 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 115655 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide 1232909553 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 1236259553 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7602399187 # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total 7602399187 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 8835308740 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 8838877740 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 8835308740 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total 8838877740 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 138731.805221 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 138531.998319 # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71231.534246 # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71231.534246 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 76420.090300 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 76424.518957 # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 1575605 # number of replacements
system.l2c.tags.tagsinuse 65208.311267 # Cycle average of tags in use
system.l2c.tags.total_refs 6750580 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 1636875 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 4.124066 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 3024712500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 9648.504654 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 430.210636 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 509.722466 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 4113.935017 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 22579.924066 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 21373.967512 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.667516 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker 13.437669 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 2580.265558 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 2788.873436 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1154.802739 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.147224 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006564 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.007778 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.062774 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.344542 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.326141 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker 0.000205 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.039372 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.042555 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.017621 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022 10940 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023 249 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 50081 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2 103 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3 404 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4 10423 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 244 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2182 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 3614 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 44004 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022 0.166931 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023 0.003799 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.764175 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 76956529 # Number of tag accesses
system.l2c.tags.data_accesses 76956529 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 2841841 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 2841841 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 3 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 3 # number of WritebackClean hits
system.l2c.UpgradeReq_hits::cpu0.data 208782 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 171973 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 380755 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data 54097 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data 47819 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 101916 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 54890 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 53294 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 108184 # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12794 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5104 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst 534660 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data 628574 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 294599 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11629 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5041 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst 480238 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data 542860 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283154 # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total 2798653 # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data 134880 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data 130480 # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total 265360 # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker 12794 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 5104 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 534660 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 683464 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher 294599 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 11629 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 5041 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 480238 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 596154 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher 283154 # number of demand (read+write) hits
system.l2c.demand_hits::total 2906837 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 12794 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 5104 # number of overall hits
system.l2c.overall_hits::cpu0.inst 534660 # number of overall hits
system.l2c.overall_hits::cpu0.data 683464 # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher 294599 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 11629 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 5041 # number of overall hits
system.l2c.overall_hits::cpu1.inst 480238 # number of overall hits
system.l2c.overall_hits::cpu1.data 596154 # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher 283154 # number of overall hits
system.l2c.overall_hits::total 2906837 # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data 24185 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 25856 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 50041 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data 906 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data 988 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 1894 # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 87757 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 47516 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 135273 # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3402 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3300 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst 61095 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data 168033 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 329831 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1494 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker 962 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst 49649 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data 109122 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 190278 # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total 917166 # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data 463890 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data 106177 # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total 570067 # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker 3402 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 3300 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 61095 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 255790 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher 329831 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1494 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker 962 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 49649 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 156638 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher 190278 # number of demand (read+write) misses
system.l2c.demand_misses::total 1052439 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 3402 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 3300 # number of overall misses
system.l2c.overall_misses::cpu0.inst 61095 # number of overall misses
system.l2c.overall_misses::cpu0.data 255790 # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher 329831 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1494 # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker 962 # number of overall misses
system.l2c.overall_misses::cpu1.inst 49649 # number of overall misses
system.l2c.overall_misses::cpu1.data 156638 # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher 190278 # number of overall misses
system.l2c.overall_misses::total 1052439 # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data 155584500 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 165207000 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 320791500 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data 10231000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data 8907000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 19138000 # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data 8384405997 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 4313472997 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 12697878994 # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 311169000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 297359500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5460514000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data 16355884996 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 47369049298 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 141229500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 92798500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4383525500 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data 10640360000 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 27539015255 # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 112590905549 # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data 36778500 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data 35261000 # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total 72039500 # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker 311169000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker 297359500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst 5460514000 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data 24740290993 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 47369049298 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 141229500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker 92798500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 4383525500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 14953832997 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 27539015255 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 125288784543 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker 311169000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker 297359500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst 5460514000 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data 24740290993 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 47369049298 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 141229500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker 92798500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 4383525500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 14953832997 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 27539015255 # number of overall miss cycles
system.l2c.overall_miss_latency::total 125288784543 # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks 2841841 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total 2841841 # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackClean_accesses::writebacks 3 # number of WritebackClean accesses(hits+misses)
system.l2c.WritebackClean_accesses::total 3 # number of WritebackClean accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 232967 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 197829 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 430796 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data 55003 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data 48807 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 103810 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 142647 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 100810 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 243457 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 16196 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8404 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst 595755 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data 796607 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 624430 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 13123 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6003 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst 529887 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data 651982 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 473432 # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total 3715819 # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data 598770 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data 236657 # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total 835427 # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 16196 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 8404 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 595755 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 939254 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher 624430 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 13123 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 6003 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 529887 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 752792 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher 473432 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 3959276 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 16196 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 8404 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 595755 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 939254 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher 624430 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 13123 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 6003 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 529887 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 752792 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher 473432 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 3959276 # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.103813 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.130699 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.116159 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016472 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020243 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.018245 # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.615204 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.471342 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.555634 # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.210052 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.392670 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102551 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.210936 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.528211 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.113846 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.160253 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.093697 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.167370 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.401912 # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total 0.246827 # miss rate for ReadSharedReq accesses
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system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.167324 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246754 # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.774738 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.448654 # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total 0.682366 # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.210052 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.392670 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102354 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.272313 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.528211 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.208036 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.265748 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.210052 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.392670 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102354 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.272313 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.528211 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.113846 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.160253 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.093499 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.208036 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.401912 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.265748 # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20007.215133 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20922.435798 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20480.106273 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24467.990066 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24337.044534 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24399.682682 # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 85540.175428 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80775.672510 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 83866.595921 # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 87340.145476 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 87513.582380 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 112772.350532 # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24895.958354 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20717.471769 # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 24117.700412 # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81466.490300 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80108.939394 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 79397.611466 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 86722.561889 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133615.676277 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 84530.456493 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 86464.137214 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 78311.895891 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85469.251788 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134729.425703 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 109056.054139 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162146.824876 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149138.789590 # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 122053.187311 # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63058.493402 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 77125.713494 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 65389.705882 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77908.870645 # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 74383.639767 # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests 3980803 # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests 2353726 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 3243 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq 59676 # Transaction distribution
system.membus.trans_dist::ReadResp 985495 # Transaction distribution
system.membus.trans_dist::WriteReq 38244 # Transaction distribution
system.membus.trans_dist::WriteResp 38244 # Transaction distribution
system.membus.trans_dist::WritebackDirty 1315010 # Transaction distribution
system.membus.trans_dist::CleanEvict 256715 # Transaction distribution
system.membus.trans_dist::UpgradeReq 339680 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 271581 # Transaction distribution
system.membus.trans_dist::UpgradeResp 24 # Transaction distribution
system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution
system.membus.trans_dist::ReadExReq 147332 # Transaction distribution
system.membus.trans_dist::ReadExResp 134542 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 925819 # Transaction distribution
system.membus.trans_dist::InvalidateReq 674453 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122580 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4797896 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 4945870 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 237932 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 5183802 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155710 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144939472 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total 145146374 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7255040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 7255040 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 152401414 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 572055 # Total snoops (count)
system.membus.snoopTraffic 191360 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 2456788 # Request fanout histogram
system.membus.snoop_fanout::mean 0.015156 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.122173 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 2419553 98.48% 98.48% # Request fanout histogram
system.membus.snoop_fanout::1 37235 1.52% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2456788 # Request fanout histogram
system.membus.reqLayer0.occupancy 98064494 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 21142497 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 9055699898 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer2.occupancy 5680392120 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 45554532 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks
system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks
system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks
system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks
system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks
system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets 3 # Total Packets
system.realview.ethernet.totBytes 966 # Total Bytes
system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks
system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks
system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks
system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests 11893981 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 6468498 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1904661 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 211231 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 193743 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 17488 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47383917710000 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq 59678 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 4527289 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 38244 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 38244 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 4050158 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 2718586 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 717362 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 373497 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1090859 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 293033 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 293033 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 4468431 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 869390 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp 835427 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9945746 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7459601 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 17405347 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 252717925 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 183230753 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 435948678 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 2969827 # Total snoops (count)
system.toL2Bus.snoopTraffic 128627856 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 8396274 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 0.355668 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0.483046 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 5427479 64.64% 64.64% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 2951307 35.15% 99.79% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 17488 0.21% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 8396274 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 9289434840 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 2606647 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 4518737086 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 3678115853 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 5420 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 13392 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
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