2378 lines
274 KiB
Plaintext
2378 lines
274 KiB
Plaintext
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---------- Begin Simulation Statistics ----------
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sim_seconds 1.906534 # Number of seconds simulated
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sim_ticks 1906533530000 # Number of ticks simulated
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final_tick 1906533530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 134861 # Simulator instruction rate (inst/s)
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host_op_rate 134861 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4533949866 # Simulator tick rate (ticks/s)
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host_mem_usage 343876 # Number of bytes of host memory used
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host_seconds 420.50 # Real time elapsed on the host
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sim_insts 56709432 # Number of instructions simulated
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sim_ops 56709432 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
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system.physmem.bytes_read::cpu0.inst 896192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 24492096 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 81664 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 812544 # Number of bytes read from this memory
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system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
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system.physmem.bytes_read::total 26283456 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 896192 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 81664 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 977856 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7904832 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7904832 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.inst 14003 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 382689 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 1276 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 12696 # Number of read requests responded to by this memory
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system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 410679 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 123513 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 123513 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 470064 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 12846402 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 42834 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 426189 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 13785992 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 470064 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 42834 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 512897 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 4146180 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 4146180 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 4146180 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 470064 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 12846402 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 42834 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 426189 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 17932172 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 410679 # Number of read requests accepted
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system.physmem.writeReqs 123513 # Number of write requests accepted
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system.physmem.readBursts 410679 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 123513 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 26276352 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue
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system.physmem.bytesWritten 7903488 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 26283456 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 7904832 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 26110 # Per bank write bursts
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system.physmem.perBankRdBursts::1 26073 # Per bank write bursts
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system.physmem.perBankRdBursts::2 25765 # Per bank write bursts
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system.physmem.perBankRdBursts::3 25777 # Per bank write bursts
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system.physmem.perBankRdBursts::4 25805 # Per bank write bursts
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system.physmem.perBankRdBursts::5 25558 # Per bank write bursts
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system.physmem.perBankRdBursts::6 25453 # Per bank write bursts
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system.physmem.perBankRdBursts::7 25268 # Per bank write bursts
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system.physmem.perBankRdBursts::8 25514 # Per bank write bursts
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system.physmem.perBankRdBursts::9 25670 # Per bank write bursts
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system.physmem.perBankRdBursts::10 25901 # Per bank write bursts
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system.physmem.perBankRdBursts::11 25385 # Per bank write bursts
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system.physmem.perBankRdBursts::12 25810 # Per bank write bursts
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system.physmem.perBankRdBursts::13 25833 # Per bank write bursts
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system.physmem.perBankRdBursts::14 25046 # Per bank write bursts
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system.physmem.perBankRdBursts::15 25600 # Per bank write bursts
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system.physmem.perBankWrBursts::0 8438 # Per bank write bursts
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system.physmem.perBankWrBursts::1 8395 # Per bank write bursts
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system.physmem.perBankWrBursts::2 7934 # Per bank write bursts
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system.physmem.perBankWrBursts::3 7573 # Per bank write bursts
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system.physmem.perBankWrBursts::4 7567 # Per bank write bursts
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system.physmem.perBankWrBursts::5 7501 # Per bank write bursts
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system.physmem.perBankWrBursts::6 7444 # Per bank write bursts
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system.physmem.perBankWrBursts::7 7061 # Per bank write bursts
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system.physmem.perBankWrBursts::8 7349 # Per bank write bursts
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system.physmem.perBankWrBursts::9 7703 # Per bank write bursts
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system.physmem.perBankWrBursts::10 7693 # Per bank write bursts
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system.physmem.perBankWrBursts::11 7415 # Per bank write bursts
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system.physmem.perBankWrBursts::12 7960 # Per bank write bursts
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system.physmem.perBankWrBursts::13 8226 # Per bank write bursts
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system.physmem.perBankWrBursts::14 7426 # Per bank write bursts
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system.physmem.perBankWrBursts::15 7807 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 24 # Number of times write queue was full causing retry
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system.physmem.totGap 1906529083500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 410679 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 123513 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 317651 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 38167 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 29690 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 24938 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 89 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 15 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 6 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 2892 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 3447 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 4536 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 6150 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 6970 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 8000 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 9213 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 7568 # What write queue length does an incoming req see
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|
system.physmem.wrQLenPdf::24 8228 # What write queue length does an incoming req see
|
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system.physmem.wrQLenPdf::25 9103 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 8348 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 7491 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 7850 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 8309 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 6391 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 6719 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 6204 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 301 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 188 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 199 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 178 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 121 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 116 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 109 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 149 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 133 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 136 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 201 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 187 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 211 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 171 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 206 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 130 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 140 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 137 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 137 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 119 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 101 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 124 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 81 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 65 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 38 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 64501 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 529.911784 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 323.379229 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 416.310744 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 14472 22.44% 22.44% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 11319 17.55% 39.99% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 5673 8.80% 48.78% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2735 4.24% 53.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2521 3.91% 56.93% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1561 2.42% 59.35% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::768-895 1592 2.47% 61.82% # Bytes accessed per row activation
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|
system.physmem.bytesPerActivate::896-1023 1422 2.20% 64.02% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 23206 35.98% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 64501 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5582 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 73.544966 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::stdev 2807.309852 # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::0-8191 5579 99.95% 99.95% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
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|
system.physmem.rdPerTurnAround::total 5582 # Reads before turning the bus around for writes
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|
system.physmem.wrPerTurnAround::samples 5582 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::mean 22.123253 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 18.862531 # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::stdev 21.587113 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 4829 86.51% 86.51% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 142 2.54% 89.05% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 15 0.27% 89.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 29 0.52% 89.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 220 3.94% 93.78% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 21 0.38% 94.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 13 0.23% 94.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 6 0.11% 94.50% # Writes before turning the bus around for reads
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|
system.physmem.wrPerTurnAround::48-51 3 0.05% 94.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 8 0.14% 94.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 8 0.14% 94.84% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 7 0.13% 94.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 7 0.13% 95.09% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 3 0.05% 95.15% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 1 0.02% 95.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 1 0.02% 95.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 21 0.38% 95.56% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::84-87 2 0.04% 95.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 16 0.29% 95.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::92-95 1 0.02% 95.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 179 3.21% 99.10% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::100-103 2 0.04% 99.14% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 1 0.02% 99.16% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 3 0.05% 99.21% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::116-119 2 0.04% 99.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::120-123 1 0.02% 99.27% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::124-127 1 0.02% 99.28% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 5 0.09% 99.37% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.39% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.02% 99.41% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::148-151 1 0.02% 99.43% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.02% 99.44% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::156-159 2 0.04% 99.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::172-175 6 0.11% 99.59% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::184-187 3 0.05% 99.64% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::188-191 1 0.02% 99.66% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::192-195 2 0.04% 99.70% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::196-199 2 0.04% 99.73% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::212-215 1 0.02% 99.75% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::216-219 1 0.02% 99.77% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::224-227 13 0.23% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 5582 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 4047296750 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 11745446750 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 2052840000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 9857.80 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 28607.80 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 13.78 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 4.15 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 13.79 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 4.15 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.14 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 2.26 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 26.95 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 369870 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 99689 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 80.71 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 3568995.95 # Average gap between requests
|
|
system.physmem.pageHitRate 87.92 # Row buffer hit rate, read and write combined
|
|
system.physmem_0.actEnergy 245828520 # Energy for activate commands per rank (pJ)
|
|
system.physmem_0.preEnergy 134132625 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_0.readEnergy 1605310200 # Energy for read commands per rank (pJ)
|
|
system.physmem_0.writeEnergy 401196240 # Energy for write commands per rank (pJ)
|
|
system.physmem_0.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_0.actBackEnergy 58054066515 # Energy for active background per rank (pJ)
|
|
system.physmem_0.preBackEnergy 1092995561250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_0.totalEnergy 1277961588390 # Total energy per rank (pJ)
|
|
system.physmem_0.averagePower 670.306343 # Core power per rank (mW)
|
|
system.physmem_0.memoryStateTime::IDLE 1818124535500 # Time in different power states
|
|
system.physmem_0.memoryStateTime::REF 63663080000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 24745773250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 241799040 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 131934000 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 1597120200 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 399031920 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 124525493040 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 57215830500 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 1093730864250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 1277842072950 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 670.243651 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 1819353589250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 63663080000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 23516733250 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.bridge.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.branchPred.lookups 16961800 # Number of BP lookups
|
|
system.cpu0.branchPred.condPredicted 14485891 # Number of conditional branches predicted
|
|
system.cpu0.branchPred.condIncorrect 473040 # Number of conditional branches incorrect
|
|
system.cpu0.branchPred.BTBLookups 10754552 # Number of BTB lookups
|
|
system.cpu0.branchPred.BTBHits 4802971 # Number of BTB hits
|
|
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu0.branchPred.BTBHitPct 44.659889 # BTB Hit Percentage
|
|
system.cpu0.branchPred.usedRAS 946597 # Number of times the RAS was used to get a target.
|
|
system.cpu0.branchPred.RASInCorrect 35405 # Number of incorrect RAS predictions.
|
|
system.cpu0.branchPred.indirectLookups 5065158 # Number of indirect predictor lookups.
|
|
system.cpu0.branchPred.indirectHits 501808 # Number of indirect target hits.
|
|
system.cpu0.branchPred.indirectMisses 4563350 # Number of indirect misses.
|
|
system.cpu0.branchPredindirectMispredicted 210940 # Number of mispredicted indirect branches.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu0.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu0.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu0.dtb.read_hits 9542415 # DTB read hits
|
|
system.cpu0.dtb.read_misses 34570 # DTB read misses
|
|
system.cpu0.dtb.read_acv 614 # DTB read access violations
|
|
system.cpu0.dtb.read_accesses 570502 # DTB read accesses
|
|
system.cpu0.dtb.write_hits 5776455 # DTB write hits
|
|
system.cpu0.dtb.write_misses 8473 # DTB write misses
|
|
system.cpu0.dtb.write_acv 390 # DTB write access violations
|
|
system.cpu0.dtb.write_accesses 186760 # DTB write accesses
|
|
system.cpu0.dtb.data_hits 15318870 # DTB hits
|
|
system.cpu0.dtb.data_misses 43043 # DTB misses
|
|
system.cpu0.dtb.data_acv 1004 # DTB access violations
|
|
system.cpu0.dtb.data_accesses 757262 # DTB accesses
|
|
system.cpu0.itb.fetch_hits 1323023 # ITB hits
|
|
system.cpu0.itb.fetch_misses 7096 # ITB misses
|
|
system.cpu0.itb.fetch_acv 610 # ITB acv
|
|
system.cpu0.itb.fetch_accesses 1330119 # ITB accesses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.read_acv 0 # DTB read access violations
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.write_acv 0 # DTB write access violations
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.data_hits 0 # DTB hits
|
|
system.cpu0.itb.data_misses 0 # DTB misses
|
|
system.cpu0.itb.data_acv 0 # DTB access violations
|
|
system.cpu0.itb.data_accesses 0 # DTB accesses
|
|
system.cpu0.numPwrStateTransitions 13007 # Number of power state transitions
|
|
system.cpu0.pwrStateClkGateDist::samples 6504 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::mean 284289977.091175 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::stdev 440390387.503353 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::underflows 1 0.02% 0.02% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::1000-5e+10 6503 99.98% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateClkGateDist::total 6504 # Distribution of time spent in the clock gated state
|
|
system.cpu0.pwrStateResidencyTicks::ON 57511518999 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.pwrStateResidencyTicks::CLK_GATED 1849022011001 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.numCycles 115029541 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.fetch.icacheStallCycles 26105514 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu0.fetch.Insts 74391279 # Number of instructions fetch has processed
|
|
system.cpu0.fetch.Branches 16961800 # Number of branches that fetch encountered
|
|
system.cpu0.fetch.predictedBranches 6251376 # Number of branches that fetch has predicted taken
|
|
system.cpu0.fetch.Cycles 82220028 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu0.fetch.SquashCycles 1360432 # Number of cycles fetch has spent squashing
|
|
system.cpu0.fetch.TlbCycles 20 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu0.fetch.MiscStallCycles 28534 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu0.fetch.PendingTrapStallCycles 140847 # Number of stall cycles due to pending traps
|
|
system.cpu0.fetch.PendingQuiesceStallCycles 424678 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu0.fetch.IcacheWaitRetryStallCycles 286 # Number of stall cycles due to full MSHR
|
|
system.cpu0.fetch.CacheLines 8564382 # Number of cache lines fetched
|
|
system.cpu0.fetch.IcacheSquashes 320281 # Number of outstanding Icache misses that were squashed
|
|
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu0.fetch.rateDist::samples 109600123 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::mean 0.678752 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::stdev 2.000671 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::0 95795479 87.40% 87.40% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::1 897061 0.82% 88.22% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::2 1880834 1.72% 89.94% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::3 785387 0.72% 90.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::4 2637004 2.41% 93.06% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::5 588358 0.54% 93.60% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::6 697546 0.64% 94.23% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::7 846325 0.77% 95.01% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::8 5472129 4.99% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.rateDist::total 109600123 # Number of instructions fetched each cycle (Total)
|
|
system.cpu0.fetch.branchRate 0.147456 # Number of branch fetches per cycle
|
|
system.cpu0.fetch.rate 0.646715 # Number of inst fetches per cycle
|
|
system.cpu0.decode.IdleCycles 20981522 # Number of cycles decode is idle
|
|
system.cpu0.decode.BlockedCycles 77286866 # Number of cycles decode is blocked
|
|
system.cpu0.decode.RunCycles 8861450 # Number of cycles decode is running
|
|
system.cpu0.decode.UnblockCycles 1818601 # Number of cycles decode is unblocking
|
|
system.cpu0.decode.SquashCycles 651683 # Number of cycles decode is squashing
|
|
system.cpu0.decode.BranchResolved 621495 # Number of times decode resolved a branch
|
|
system.cpu0.decode.BranchMispred 29133 # Number of times decode detected a branch misprediction
|
|
system.cpu0.decode.DecodedInsts 64563390 # Number of instructions handled by decode
|
|
system.cpu0.decode.SquashedInsts 88112 # Number of squashed instructions handled by decode
|
|
system.cpu0.rename.SquashCycles 651683 # Number of cycles rename is squashing
|
|
system.cpu0.rename.IdleCycles 21851256 # Number of cycles rename is idle
|
|
system.cpu0.rename.BlockCycles 51776932 # Number of cycles rename is blocking
|
|
system.cpu0.rename.serializeStallCycles 17156942 # count of cycles rename stalled for serializing inst
|
|
system.cpu0.rename.RunCycles 9742291 # Number of cycles rename is running
|
|
system.cpu0.rename.UnblockCycles 8421017 # Number of cycles rename is unblocking
|
|
system.cpu0.rename.RenamedInsts 62086646 # Number of instructions processed by rename
|
|
system.cpu0.rename.ROBFullEvents 197170 # Number of times rename has blocked due to ROB full
|
|
system.cpu0.rename.IQFullEvents 2004328 # Number of times rename has blocked due to IQ full
|
|
system.cpu0.rename.LQFullEvents 218757 # Number of times rename has blocked due to LQ full
|
|
system.cpu0.rename.SQFullEvents 4545100 # Number of times rename has blocked due to SQ full
|
|
system.cpu0.rename.RenamedOperands 41879351 # Number of destination operands rename has renamed
|
|
system.cpu0.rename.RenameLookups 74952395 # Number of register rename lookups that rename has made
|
|
system.cpu0.rename.int_rename_lookups 74819888 # Number of integer rename lookups
|
|
system.cpu0.rename.fp_rename_lookups 123702 # Number of floating rename lookups
|
|
system.cpu0.rename.CommittedMaps 34134806 # Number of HB maps that are committed
|
|
system.cpu0.rename.UndoneMaps 7744545 # Number of HB maps that are undone due to squashing
|
|
system.cpu0.rename.serializingInsts 1440211 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 234687 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 12404512 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 9945616 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 6151141 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 1474462 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 959878 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 54892526 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 1879962 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 53219239 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 73531 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 9606336 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 4159079 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 1308684 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 109600123 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 0.485576 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.229164 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 87964311 80.26% 80.26% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 9240201 8.43% 88.69% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 3866881 3.53% 92.22% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 2775272 2.53% 94.75% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 2892547 2.64% 97.39% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 1421694 1.30% 98.69% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 953270 0.87% 99.56% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 366394 0.33% 99.89% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 119553 0.11% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 109600123 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 170160 16.71% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 1 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 16.71% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 520319 51.11% 67.82% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 327644 32.18% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 2537 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 36500931 68.59% 68.59% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 56437 0.11% 68.70% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.70% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 25510 0.05% 68.74% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.74% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.74% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.74% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 1267 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.75% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 9976302 18.75% 87.49% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 5867670 11.03% 98.52% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 788585 1.48% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 53219239 # Type of FU issued
|
|
system.cpu0.iq.rate 0.462657 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 1018124 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.019131 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 216556534 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 66119650 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 51474452 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 573722 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 277081 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 260310 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 53925009 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 309817 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 608784 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 1996070 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 4265 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 18313 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 688901 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 18448 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 363376 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 651683 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 48679015 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 759858 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 60350483 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 162315 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 9945616 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 6151141 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 1664805 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 40490 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 518912 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 18313 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 186521 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 513145 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 699666 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 52530190 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 9602772 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 689049 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 3577995 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 15404618 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 8349417 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 5801846 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 0.456667 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 51922146 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 51734762 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 26504573 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 36648490 # num instructions consuming a value
|
|
system.cpu0.iew.wb_rate 0.449752 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.723211 # average fanout of values written-back
|
|
system.cpu0.commit.commitSquashedInsts 10116425 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 571278 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 623596 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 107842796 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 0.464314 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 1.394503 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 90117032 83.56% 83.56% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 7061240 6.55% 90.11% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 3809100 3.53% 93.64% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 2021336 1.87% 95.52% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 1578999 1.46% 96.98% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 575276 0.53% 97.52% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 421394 0.39% 97.91% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 458654 0.43% 98.33% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 1799765 1.67% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 107842796 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 50072886 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 50072886 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 13411786 # Number of memory references committed
|
|
system.cpu0.commit.loads 7949546 # Number of loads committed
|
|
system.cpu0.commit.membars 194670 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 7579863 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 251347 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 46348996 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 640938 # Number of function calls committed.
|
|
system.cpu0.commit.op_class_0::No_OpClass 2909270 5.81% 5.81% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntAlu 32681197 65.27% 71.08% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntMult 55117 0.11% 71.19% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.19% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatAdd 25038 0.05% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatDiv 1267 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.24% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemRead 8144216 16.26% 87.50% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::MemWrite 5468196 10.92% 98.43% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::IprAccess 788585 1.57% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu0.commit.op_class_0::total 50072886 # Class of committed instruction
|
|
system.cpu0.commit.bw_lim_events 1799765 # number cycles where commit BW limit reached
|
|
system.cpu0.rob.rob_reads 166055766 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 122136916 # The number of ROB writes
|
|
system.cpu0.timesIdled 488999 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 5429418 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.quiesceCycles 3697477415 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu0.committedInsts 47166151 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 47166151 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.cpi 2.438816 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 2.438816 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 0.410035 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 0.410035 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 68768616 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 37693548 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 122704 # number of floating regfile reads
|
|
system.cpu0.fp_regfile_writes 131478 # number of floating regfile writes
|
|
system.cpu0.misc_regfile_reads 1676808 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 792469 # number of misc regfile writes
|
|
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.tags.replacements 1260860 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 506.428743 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 10814422 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 1261290 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 8.574096 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 26822500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.428743 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.989119 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.989119 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 412 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.839844 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 57625075 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 57625075 # Number of data accesses
|
|
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 6881291 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 6881291 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 3568585 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 3568585 # number of WriteReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 177059 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 177059 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 182551 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 182551 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 10449876 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 10449876 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 10449876 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 10449876 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 1562512 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 1562512 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 1693924 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1693924 # number of WriteReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20209 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 20209 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2828 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 2828 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 3256436 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 3256436 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 3256436 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 3256436 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 38980676000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 38980676000 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 74553561151 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 74553561151 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 291267500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 291267500 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 15945500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 15945500 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 113534237151 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 113534237151 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 113534237151 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 113534237151 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 8443803 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 8443803 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 5262509 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 5262509 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 197268 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 197268 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 185379 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 185379 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 13706312 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 13706312 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 13706312 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 13706312 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.185048 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.185048 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.321885 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.321885 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.102444 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.102444 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.015255 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.015255 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.237587 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.237587 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.237587 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.237587 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24947.441044 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 24947.441044 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44012.341257 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 44012.341257 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14412.761641 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14412.761641 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5638.437058 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5638.437058 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 34864.568857 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34864.568857 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 34864.568857 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 4192146 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 2471 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 109181 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 83 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.396296 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 29.771084 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.writebacks::writebacks 743371 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 743371 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 555767 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 555767 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1440437 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1440437 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5460 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5460 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 1996204 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1996204 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 1996204 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1996204 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1006745 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 1006745 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 253487 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 253487 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14749 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14749 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2828 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2828 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 1260232 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 1260232 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1260232 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 1260232 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7013 # number of ReadReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10003 # number of WriteReq MSHR uncacheable
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17016 # number of overall MSHR uncacheable misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 29619600000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 29619600000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11703772725 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11703772725 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170858500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170858500 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 13117500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 13117500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 41323372725 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 41323372725 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 41323372725 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 41323372725 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1563340000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1563340000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1563340000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1563340000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.119229 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.119229 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048168 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048168 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.074766 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.074766 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.015255 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.015255 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.091945 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.091945 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.091945 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29421.154314 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29421.154314 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 46171.096447 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46171.096447 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11584.412503 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11584.412503 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4638.437058 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4638.437058 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 32790.289982 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 32790.289982 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222920.290888 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222920.290888 # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 91874.706159 # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 91874.706159 # average overall mshr uncacheable latency
|
|
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.tags.replacements 908505 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 509.512047 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 7601055 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 909016 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 8.361850 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 28452405500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.512047 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995141 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.995141 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 9473645 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 9473645 # Number of data accesses
|
|
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 7601055 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 7601055 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 7601055 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 7601055 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 7601055 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 7601055 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 963326 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 963326 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 963326 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 963326 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 963326 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 963326 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13819823495 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 13819823495 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 13819823495 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 13819823495 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 13819823495 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 13819823495 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 8564381 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 8564381 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 8564381 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 8564381 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 8564381 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 8564381 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112481 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.112481 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112481 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.112481 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112481 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.112481 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14345.946746 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 14345.946746 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 14345.946746 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14345.946746 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 14345.946746 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 6257 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 203 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 30.822660 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.writebacks::writebacks 908505 # number of writebacks
|
|
system.cpu0.icache.writebacks::total 908505 # number of writebacks
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54062 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 54062 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 54062 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 54062 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 54062 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 54062 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 909264 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 909264 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 909264 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 909264 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 909264 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 909264 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 12278033496 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 12278033496 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 12278033496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 12278033496 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 12278033496 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 12278033496 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.106168 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.106168 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.106168 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.106168 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13503.265824 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13503.265824 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 13503.265824 # average overall mshr miss latency
|
|
system.cpu1.branchPred.lookups 4250134 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 3659200 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 108723 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 2354380 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 849662 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 36.088567 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 217108 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 8204 # Number of incorrect RAS predictions.
|
|
system.cpu1.branchPred.indirectLookups 1308734 # Number of indirect predictor lookups.
|
|
system.cpu1.branchPred.indirectHits 157441 # Number of indirect target hits.
|
|
system.cpu1.branchPred.indirectMisses 1151293 # Number of indirect misses.
|
|
system.cpu1.branchPredindirectMispredicted 37897 # Number of mispredicted indirect branches.
|
|
system.cpu1.dtb.fetch_hits 0 # ITB hits
|
|
system.cpu1.dtb.fetch_misses 0 # ITB misses
|
|
system.cpu1.dtb.fetch_acv 0 # ITB acv
|
|
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
|
|
system.cpu1.dtb.read_hits 2331871 # DTB read hits
|
|
system.cpu1.dtb.read_misses 15400 # DTB read misses
|
|
system.cpu1.dtb.read_acv 73 # DTB read access violations
|
|
system.cpu1.dtb.read_accesses 429786 # DTB read accesses
|
|
system.cpu1.dtb.write_hits 1381774 # DTB write hits
|
|
system.cpu1.dtb.write_misses 3743 # DTB write misses
|
|
system.cpu1.dtb.write_acv 71 # DTB write access violations
|
|
system.cpu1.dtb.write_accesses 161427 # DTB write accesses
|
|
system.cpu1.dtb.data_hits 3713645 # DTB hits
|
|
system.cpu1.dtb.data_misses 19143 # DTB misses
|
|
system.cpu1.dtb.data_acv 144 # DTB access violations
|
|
system.cpu1.dtb.data_accesses 591213 # DTB accesses
|
|
system.cpu1.itb.fetch_hits 662529 # ITB hits
|
|
system.cpu1.itb.fetch_misses 3380 # ITB misses
|
|
system.cpu1.itb.fetch_acv 133 # ITB acv
|
|
system.cpu1.itb.fetch_accesses 665909 # ITB accesses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.read_acv 0 # DTB read access violations
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.write_acv 0 # DTB write access violations
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.data_hits 0 # DTB hits
|
|
system.cpu1.itb.data_misses 0 # DTB misses
|
|
system.cpu1.itb.data_acv 0 # DTB access violations
|
|
system.cpu1.itb.data_accesses 0 # DTB accesses
|
|
system.cpu1.numPwrStateTransitions 4980 # Number of power state transitions
|
|
system.cpu1.pwrStateClkGateDist::samples 2490 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::mean 762354971.285141 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::stdev 386526411.344669 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::1000-5e+10 2490 100.00% 100.00% # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::min_value 400000 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::max_value 975501000 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateClkGateDist::total 2490 # Distribution of time spent in the clock gated state
|
|
system.cpu1.pwrStateResidencyTicks::ON 8269651500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.pwrStateResidencyTicks::CLK_GATED 1898263878500 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.numCycles 16541794 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 6749073 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 16895090 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 4250134 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 1224211 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 8698208 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 363130 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.MiscStallCycles 26231 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.PendingTrapStallCycles 65753 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.PendingQuiesceStallCycles 47571 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu1.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR
|
|
system.cpu1.fetch.CacheLines 1900929 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 80768 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 15768440 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.071450 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.476995 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 12797159 81.16% 81.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 186632 1.18% 82.34% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 321640 2.04% 84.38% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 225512 1.43% 85.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 384419 2.44% 88.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 144313 0.92% 89.16% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 169042 1.07% 90.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 202635 1.29% 91.52% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 1337088 8.48% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 15768440 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.256933 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.021358 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 5523877 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 7693314 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 2103455 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 273251 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 174542 # Number of cycles decode is squashing
|
|
system.cpu1.decode.BranchResolved 146034 # Number of times decode resolved a branch
|
|
system.cpu1.decode.BranchMispred 7171 # Number of times decode detected a branch misprediction
|
|
system.cpu1.decode.DecodedInsts 13792543 # Number of instructions handled by decode
|
|
system.cpu1.decode.SquashedInsts 22640 # Number of squashed instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 174542 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 5705734 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 782365 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 5725411 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 2195690 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 1184696 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 13060888 # Number of instructions processed by rename
|
|
system.cpu1.rename.ROBFullEvents 4153 # Number of times rename has blocked due to ROB full
|
|
system.cpu1.rename.IQFullEvents 107025 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LQFullEvents 30497 # Number of times rename has blocked due to LQ full
|
|
system.cpu1.rename.SQFullEvents 586772 # Number of times rename has blocked due to SQ full
|
|
system.cpu1.rename.RenamedOperands 8670673 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 15585724 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 15521516 # Number of integer rename lookups
|
|
system.cpu1.rename.fp_rename_lookups 57730 # Number of floating rename lookups
|
|
system.cpu1.rename.CommittedMaps 6788049 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 1882616 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 491915 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 50500 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 2201368 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 2434805 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 1482534 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 303562 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 164759 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 11452007 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 560044 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 10991859 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 27120 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 2468765 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 1174488 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 414117 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 15768440 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 0.697080 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.421678 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 11265469 71.44% 71.44% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 1937394 12.29% 83.73% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 827410 5.25% 88.98% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 596936 3.79% 92.76% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 547934 3.47% 96.24% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 289502 1.84% 98.07% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 188780 1.20% 99.27% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 83209 0.53% 99.80% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 31806 0.20% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 15768440 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 32091 10.27% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 10.27% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 173932 55.66% 65.93% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 106485 34.07% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 4751 0.04% 0.04% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 6803980 61.90% 61.94% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 16523 0.15% 62.09% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.09% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 13867 0.13% 62.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.22% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 2375 0.02% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.24% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 2450394 22.29% 84.53% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 1410696 12.83% 97.37% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 289273 2.63% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 10991859 # Type of FU issued
|
|
system.cpu1.iq.rate 0.664490 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 312508 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.028431 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 37874505 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 14381418 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 10489971 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 217280 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 104295 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 101356 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 11183979 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 115637 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 113432 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 527848 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 1066 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 5067 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 174171 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 475 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 99025 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 174542 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 497039 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 226226 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 12632900 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 57966 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 2434805 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 1482534 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 508876 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 6584 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 218362 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 5067 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 44763 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 141821 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 186584 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 10809707 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 2356029 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 182151 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 620849 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 3747857 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 1612675 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 1391828 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 0.653479 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 10644010 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 10591327 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 5073681 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 7144079 # num instructions consuming a value
|
|
system.cpu1.iew.wb_rate 0.640277 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.710194 # average fanout of values written-back
|
|
system.cpu1.commit.commitSquashedInsts 2479122 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 145927 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 162123 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 15327061 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 0.652859 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 1.628724 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 11704556 76.37% 76.37% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 1675096 10.93% 87.29% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 596024 3.89% 91.18% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 370132 2.41% 93.60% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 281840 1.84% 95.44% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 119415 0.78% 96.22% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 109784 0.72% 96.93% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 115974 0.76% 97.69% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 354240 2.31% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 15327061 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 10006417 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 10006417 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 3215320 # Number of memory references committed
|
|
system.cpu1.commit.loads 1906957 # Number of loads committed
|
|
system.cpu1.commit.membars 46297 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 1432968 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 99355 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 9296453 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 155642 # Number of function calls committed.
|
|
system.cpu1.commit.op_class_0::No_OpClass 467886 4.68% 4.68% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntAlu 5954632 59.51% 64.18% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntMult 16225 0.16% 64.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatAdd 13860 0.14% 64.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.48% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatDiv 2375 0.02% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.51% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemRead 1953254 19.52% 84.03% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::MemWrite 1308912 13.08% 97.11% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::IprAccess 289273 2.89% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu1.commit.op_class_0::total 10006417 # Class of committed instruction
|
|
system.cpu1.commit.bw_lim_events 354240 # number cycles where commit BW limit reached
|
|
system.cpu1.rob.rob_reads 27350454 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 25410376 # The number of ROB writes
|
|
system.cpu1.timesIdled 127916 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 773354 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 3796525267 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 9543281 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 9543281 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.cpi 1.733345 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 1.733345 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 0.576919 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 0.576919 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 13915898 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 7574327 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_reads 57027 # number of floating regfile reads
|
|
system.cpu1.fp_regfile_writes 56084 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 548336 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 233992 # number of misc regfile writes
|
|
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dcache.tags.replacements 125899 # number of replacements
|
|
system.cpu1.dcache.tags.tagsinuse 488.643443 # Cycle average of tags in use
|
|
system.cpu1.dcache.tags.total_refs 2930828 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.tags.sampled_refs 126411 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.tags.avg_refs 23.184913 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.tags.warmup_cycle 47496090500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.tags.occ_blocks::cpu1.data 488.643443 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.tags.occ_percent::cpu1.data 0.954382 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_percent::total 0.954382 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id
|
|
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu1.dcache.tags.tag_accesses 13906652 # Number of tag accesses
|
|
system.cpu1.dcache.tags.data_accesses 13906652 # Number of data accesses
|
|
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 1865609 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 1865609 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 981966 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 981966 # number of WriteReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 38120 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.LoadLockedReq_hits::total 38120 # number of LoadLockedReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::cpu1.data 34857 # number of StoreCondReq hits
|
|
system.cpu1.dcache.StoreCondReq_hits::total 34857 # number of StoreCondReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 2847575 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 2847575 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 2847575 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 2847575 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 231819 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 231819 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 282423 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 282423 # number of WriteReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5078 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.LoadLockedReq_misses::total 5078 # number of LoadLockedReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2912 # number of StoreCondReq misses
|
|
system.cpu1.dcache.StoreCondReq_misses::total 2912 # number of StoreCondReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 514242 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 514242 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 514242 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 514242 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3027811000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 3027811000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10676531998 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 10676531998 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 51207500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_miss_latency::total 51207500 # number of LoadLockedReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 16199500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.StoreCondReq_miss_latency::total 16199500 # number of StoreCondReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 13704342998 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 13704342998 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 13704342998 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 13704342998 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 2097428 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 2097428 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 1264389 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 1264389 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 43198 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.LoadLockedReq_accesses::total 43198 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 37769 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.StoreCondReq_accesses::total 37769 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 3361817 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 3361817 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 3361817 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 3361817 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.110525 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.110525 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223367 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.223367 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.117552 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.117552 # miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.077100 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_miss_rate::total 0.077100 # miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.152965 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.152965 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.152965 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.152965 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13061.099392 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 13061.099392 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37803.337540 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 37803.337540 # average WriteReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 10084.186688 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10084.186688 # average LoadLockedReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5563.015110 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5563.015110 # average StoreCondReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 26649.598823 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26649.598823 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 26649.598823 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 625764 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 300 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 24254 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs 25.800445 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets 15.789474 # average number of cycles each access was blocked
|
|
system.cpu1.dcache.writebacks::writebacks 81179 # number of writebacks
|
|
system.cpu1.dcache.writebacks::total 81179 # number of writebacks
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 142547 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 142547 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 235954 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 235954 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 779 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.LoadLockedReq_mshr_hits::total 779 # number of LoadLockedReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 378501 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 378501 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 378501 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 378501 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 89272 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 89272 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 46469 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 46469 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4299 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4299 # number of LoadLockedReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2912 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.StoreCondReq_mshr_misses::total 2912 # number of StoreCondReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 135741 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 135741 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 135741 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 135741 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable::total 182 # number of ReadReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.WriteReq_mshr_uncacheable::total 3016 # number of WriteReq MSHR uncacheable
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3198 # number of overall MSHR uncacheable misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1142608000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1142608000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1700967690 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1700967690 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 38610000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 38610000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 13287500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 13287500 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2843575690 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 2843575690 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2843575690 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 2843575690 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 35749500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 35749500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 35749500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.overall_mshr_uncacheable_latency::total 35749500 # number of overall MSHR uncacheable cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042563 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042563 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036752 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036752 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099518 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.099518 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.077100 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.077100 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.040377 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040377 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.040377 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12799.175553 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12799.175553 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36604.353225 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 36604.353225 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8981.158409 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8981.158409 # average LoadLockedReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4563.015110 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4563.015110 # average StoreCondReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20948.539424 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20948.539424 # average overall mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 196425.824176 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 196425.824176 # average ReadReq mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 11178.705441 # average overall mshr uncacheable latency
|
|
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 11178.705441 # average overall mshr uncacheable latency
|
|
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.icache.tags.replacements 243897 # number of replacements
|
|
system.cpu1.icache.tags.tagsinuse 471.203096 # Cycle average of tags in use
|
|
system.cpu1.icache.tags.total_refs 1645008 # Total number of references to valid blocks.
|
|
system.cpu1.icache.tags.sampled_refs 244406 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.tags.avg_refs 6.730637 # Average number of references to valid blocks.
|
|
system.cpu1.icache.tags.warmup_cycle 1879506005500 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.203096 # Average occupied blocks per requestor
|
|
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920319 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_percent::total 0.920319 # Average percentage of cache occupancy
|
|
system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id
|
|
system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
|
|
system.cpu1.icache.tags.tag_accesses 2145410 # Number of tag accesses
|
|
system.cpu1.icache.tags.data_accesses 2145410 # Number of data accesses
|
|
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 1645008 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 1645008 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 1645008 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 1645008 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 1645008 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 1645008 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 255921 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 255921 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 255921 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 255921 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 255921 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 255921 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3476894499 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 3476894499 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 3476894499 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 3476894499 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 3476894499 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 3476894499 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 1900929 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 1900929 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 1900929 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 1900929 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 1900929 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 1900929 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.134629 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.134629 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.134629 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.134629 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.134629 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.134629 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13585.811633 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 13585.811633 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 13585.811633 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13585.811633 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 13585.811633 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 470 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 38 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.368421 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.writebacks::writebacks 243897 # number of writebacks
|
|
system.cpu1.icache.writebacks::total 243897 # number of writebacks
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 11440 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 11440 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 11440 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 11440 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 11440 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 11440 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 244481 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 244481 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 244481 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 244481 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 244481 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 244481 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3131245499 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 3131245499 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3131245499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 3131245499 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3131245499 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 3131245499 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.128611 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.128611 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.128611 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.128611 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12807.725341 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12807.725341 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 12807.725341 # average overall mshr miss latency
|
|
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
|
|
system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
|
|
system.disk0.dma_write_txs 395 # Number of DMA write transactions.
|
|
system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
|
|
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.iobus.trans_dist::ReadReq 7374 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 7374 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 54571 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 54571 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11828 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 40428 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83462 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.tsunami.ide.dma::total 83462 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 123890 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47312 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 73538 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.tsunami.ide.dma::total 2661656 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2735194 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 12271500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 818000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 11000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 10500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer22.occupancy 178500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 14105000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 2828000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 6057000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 90500 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 216200796 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 27409000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 41958000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.iocache.tags.replacements 41699 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.499134 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 41715 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 1712299837000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::tsunami.ide 0.499134 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::tsunami.ide 0.031196 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.031196 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 375579 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 375579 # Number of data accesses
|
|
system.iocache.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
|
|
system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
|
|
system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
|
|
system.iocache.demand_misses::tsunami.ide 41731 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses
|
|
system.iocache.overall_misses::total 41731 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::tsunami.ide 22562883 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 22562883 # number of ReadReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::tsunami.ide 4858746913 # number of WriteLineReq miss cycles
|
|
system.iocache.WriteLineReq_miss_latency::total 4858746913 # number of WriteLineReq miss cycles
|
|
system.iocache.demand_miss_latency::tsunami.ide 4881309796 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 4881309796 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::tsunami.ide 4881309796 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 4881309796 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::tsunami.ide 41731 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 41731 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::tsunami.ide 41731 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 41731 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
|
|
system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 126049.625698 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 126049.625698 # average ReadReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::tsunami.ide 116931.722011 # average WriteLineReq miss latency
|
|
system.iocache.WriteLineReq_avg_miss_latency::total 116931.722011 # average WriteLineReq miss latency
|
|
system.iocache.demand_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 116970.832139 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::tsunami.ide 116970.832139 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 116970.832139 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.writebacks::writebacks 41520 # number of writebacks
|
|
system.iocache.writebacks::total 41520 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::tsunami.ide 179 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::tsunami.ide 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.WriteLineReq_mshr_misses::total 41552 # number of WriteLineReq MSHR misses
|
|
system.iocache.demand_mshr_misses::tsunami.ide 41731 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 13612883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 13612883 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::tsunami.ide 2778734565 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.WriteLineReq_mshr_miss_latency::total 2778734565 # number of WriteLineReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::tsunami.ide 2792347448 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 2792347448 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::tsunami.ide 2792347448 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 2792347448 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses
|
|
system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 76049.625698 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 76049.625698 # average ReadReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::tsunami.ide 66873.665889 # average WriteLineReq mshr miss latency
|
|
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 66873.665889 # average WriteLineReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 66913.025041 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 66913.025041 # average overall mshr miss latency
|
|
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.l2c.tags.replacements 345621 # number of replacements
|
|
system.l2c.tags.tagsinuse 65429.949099 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 4347999 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 411104 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 10.576397 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 5987439000 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 292.894251 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5335.962916 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 58874.943819 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 203.860157 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 722.287955 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.004469 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.081420 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.898360 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.003111 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.011021 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.998382 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1024 65483 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 1723 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 1817 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 5637 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 56151 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.999191 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 38487323 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 38487323 # Number of data accesses
|
|
system.l2c.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.l2c.WritebackDirty_hits::writebacks 824550 # number of WritebackDirty hits
|
|
system.l2c.WritebackDirty_hits::total 824550 # number of WritebackDirty hits
|
|
system.l2c.WritebackClean_hits::writebacks 880861 # number of WritebackClean hits
|
|
system.l2c.WritebackClean_hits::total 880861 # number of WritebackClean hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 2842 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 1401 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 4243 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu0.data 470 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu1.data 444 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 914 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 147625 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 30184 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 177809 # number of ReadExReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu0.inst 895088 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::cpu1.inst 243149 # number of ReadCleanReq hits
|
|
system.l2c.ReadCleanReq_hits::total 1138237 # number of ReadCleanReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu0.data 727494 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::cpu1.data 80955 # number of ReadSharedReq hits
|
|
system.l2c.ReadSharedReq_hits::total 808449 # number of ReadSharedReq hits
|
|
system.l2c.demand_hits::cpu0.inst 895088 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 875119 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 243149 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 111139 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2124495 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 895088 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 875119 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 243149 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 111139 # number of overall hits
|
|
system.l2c.overall_hits::total 2124495 # number of overall hits
|
|
system.l2c.UpgradeReq_misses::cpu0.data 6 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 3 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 9 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 110021 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 11230 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 121251 # number of ReadExReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu0.inst 14005 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::cpu1.inst 1293 # number of ReadCleanReq misses
|
|
system.l2c.ReadCleanReq_misses::total 15298 # number of ReadCleanReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu0.data 272996 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::cpu1.data 1575 # number of ReadSharedReq misses
|
|
system.l2c.ReadSharedReq_misses::total 274571 # number of ReadSharedReq misses
|
|
system.l2c.demand_misses::cpu0.inst 14005 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 383017 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 1293 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 12805 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 411120 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 14005 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 383017 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 1293 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 12805 # number of overall misses
|
|
system.l2c.overall_misses::total 411120 # number of overall misses
|
|
system.l2c.UpgradeReq_miss_latency::cpu0.data 334500 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 59000 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 393500 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 9803404500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 1283749500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 11087154000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu0.inst 1179329500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::cpu1.inst 110888000 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadCleanReq_miss_latency::total 1290217500 # number of ReadCleanReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu0.data 20156491500 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::cpu1.data 149319000 # number of ReadSharedReq miss cycles
|
|
system.l2c.ReadSharedReq_miss_latency::total 20305810500 # number of ReadSharedReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 1179329500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 29959896000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 110888000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1433068500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 32683182000 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 1179329500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 29959896000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 110888000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1433068500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 32683182000 # number of overall miss cycles
|
|
system.l2c.WritebackDirty_accesses::writebacks 824550 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackDirty_accesses::total 824550 # number of WritebackDirty accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::writebacks 880861 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.WritebackClean_accesses::total 880861 # number of WritebackClean accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 2848 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 1404 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 4252 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 470 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu1.data 445 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 915 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 257646 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 41414 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 299060 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu0.inst 909093 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::cpu1.inst 244442 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadCleanReq_accesses::total 1153535 # number of ReadCleanReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu0.data 1000490 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::cpu1.data 82530 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.ReadSharedReq_accesses::total 1083020 # number of ReadSharedReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 909093 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 1258136 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 244442 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 123944 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2535615 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 909093 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 1258136 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 244442 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 123944 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2535615 # number of overall (read+write) accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.002107 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.002137 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.002117 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.002247 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.001093 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.427024 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.271164 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.405440 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.015405 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.005290 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_miss_rate::total 0.013262 # miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.272862 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.019084 # miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_miss_rate::total 0.253523 # miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.015405 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.304432 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.005290 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.103313 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.162138 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.015405 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.304432 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.005290 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.103313 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.162138 # miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 55750 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 19666.666667 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 43722.222222 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89104.848165 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 114314.292075 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 91439.691219 # average ReadExReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 84207.747233 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 85760.247486 # average ReadCleanReq miss latency
|
|
system.l2c.ReadCleanReq_avg_miss_latency::total 84338.965878 # average ReadCleanReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 73834.384020 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 94805.714286 # average ReadSharedReq miss latency
|
|
system.l2c.ReadSharedReq_avg_miss_latency::total 73954.680210 # average ReadSharedReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 84207.747233 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 78220.799599 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 85760.247486 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 111914.759859 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 79497.913018 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 84207.747233 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 78220.799599 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 85760.247486 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 111914.759859 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 79497.913018 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.writebacks::writebacks 81993 # number of writebacks
|
|
system.l2c.writebacks::total 81993 # number of writebacks
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 17 # number of ReadCleanReq MSHR hits
|
|
system.l2c.ReadCleanReq_mshr_hits::total 18 # number of ReadCleanReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits
|
|
system.l2c.CleanEvict_mshr_misses::writebacks 10 # number of CleanEvict MSHR misses
|
|
system.l2c.CleanEvict_mshr_misses::total 10 # number of CleanEvict MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 6 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 3 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 110021 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 11230 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 121251 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 14004 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1276 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadCleanReq_mshr_misses::total 15280 # number of ReadCleanReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu0.data 272996 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::cpu1.data 1575 # number of ReadSharedReq MSHR misses
|
|
system.l2c.ReadSharedReq_mshr_misses::total 274571 # number of ReadSharedReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 14004 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 383017 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 1276 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 12805 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 411102 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 14004 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 383017 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 1276 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 12805 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 411102 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7013 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::cpu1.data 182 # number of ReadReq MSHR uncacheable
|
|
system.l2c.ReadReq_mshr_uncacheable::total 7195 # number of ReadReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10003 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3016 # number of WriteReq MSHR uncacheable
|
|
system.l2c.WriteReq_mshr_uncacheable::total 13019 # number of WriteReq MSHR uncacheable
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17016 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3198 # number of overall MSHR uncacheable misses
|
|
system.l2c.overall_mshr_uncacheable_misses::total 20214 # number of overall MSHR uncacheable misses
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 274500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 57500 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 332000 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 18500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 18500 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8703194500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1171449500 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 9874644000 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 1039194500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 96887500 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadCleanReq_mshr_miss_latency::total 1136082000 # number of ReadCleanReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 17432939000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 133569000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.ReadSharedReq_mshr_miss_latency::total 17566508000 # number of ReadSharedReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 1039194500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 26136133500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 96887500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1305018500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 28577234000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 1039194500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 26136133500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 96887500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1305018500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 28577234000 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1475661000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 33474500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 1509135500 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1475661000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 33474500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 1509135500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.002107 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.002137 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.002117 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.002247 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.001093 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.427024 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.271164 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.405440 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadCleanReq_mshr_miss_rate::total 0.013246 # mshr miss rate for ReadCleanReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.272862 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.019084 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.253523 # mshr miss rate for ReadSharedReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.162131 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015404 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.304432 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005220 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.103313 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.162131 # mshr miss rate for overall accesses
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 45750 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19166.666667 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 36888.888889 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18500 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79104.848165 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 104314.292075 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 81439.691219 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 74350.916230 # average ReadCleanReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 63857.855060 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84805.714286 # average ReadSharedReq mshr miss latency
|
|
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 63978.016615 # average ReadSharedReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74206.976578 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68237.528621 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75930.642633 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 101914.759859 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 69513.731385 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 210417.938115 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 183925.824176 # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 209747.810980 # average ReadReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 86721.967560 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 10467.323327 # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total 74657.935094 # average overall mshr uncacheable latency
|
|
system.membus.snoop_filter.tot_requests 850516 # Total number of requests made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_requests 398567 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_requests 435 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
|
|
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.membus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.membus.trans_dist::ReadReq 7195 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 297176 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 13019 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 13019 # Transaction distribution
|
|
system.membus.trans_dist::WritebackDirty 123513 # Transaction distribution
|
|
system.membus.trans_dist::CleanEvict 262911 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 6111 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 4826 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 3 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 121549 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 121146 # Transaction distribution
|
|
system.membus.trans_dist::ReadSharedReq 290030 # Transaction distribution
|
|
system.membus.trans_dist::BadAddressError 49 # Transaction distribution
|
|
system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40428 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1177677 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 98 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 1218203 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83445 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 83445 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1301648 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73538 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31530048 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 31603586 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2658240 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 34261826 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 11676 # Total snoops (count)
|
|
system.membus.snoopTraffic 28672 # Total snoop traffic (bytes)
|
|
system.membus.snoop_fanout::samples 484282 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0.001355 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0.036780 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 483626 99.86% 99.86% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 656 0.14% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 484282 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 36370000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 1352579532 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 62000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 2178718000 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 960113 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.snoop_filter.tot_requests 5113699 # Total number of requests made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_requests 2556514 # Number of requests hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_requests 337557 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.snoop_filter.tot_snoops 1071 # Total number of snoops made to the snoop filter.
|
|
system.toL2Bus.snoop_filter.hit_single_snoops 1003 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
|
|
system.toL2Bus.snoop_filter.hit_multi_snoops 68 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
|
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.toL2Bus.trans_dist::ReadReq 7195 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2265500 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 13019 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 13019 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackDirty 906543 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WritebackClean 1152402 # Transaction distribution
|
|
system.toL2Bus.trans_dist::CleanEvict 825837 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 10249 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 5740 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 15989 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 300358 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 300358 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadCleanReq 1153745 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadSharedReq 1104612 # Transaction distribution
|
|
system.toL2Bus.trans_dist::BadAddressError 49 # Transaction distribution
|
|
system.toL2Bus.trans_dist::InvalidateReq 203 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 2726862 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3834313 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732820 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 401077 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 7695072 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 116326272 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 128153608 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31253696 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 13151546 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 288885122 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 379909 # Total snoops (count)
|
|
system.toL2Bus.snoopTraffic 6725760 # Total snoop traffic (bytes)
|
|
system.toL2Bus.snoop_fanout::samples 2940742 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 0.121053 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.326514 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 2585068 87.91% 87.91% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 355364 12.08% 99.99% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 309 0.01% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 1 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 2940742 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 4550461413 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 301885 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 1365446887 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 1921756875 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 368286347 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 208891088 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1906533530000 # Cumulative time (in ticks) in various power states
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 6504 # number of quiesce instructions executed
|
|
system.cpu0.kern.inst.hwrei 179089 # number of hwrei instructions executed
|
|
system.cpu0.kern.ipl_count::0 63660 40.34% 40.34% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::21 131 0.08% 40.42% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::22 1926 1.22% 41.64% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::30 175 0.11% 41.75% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::31 91921 58.25% 100.00% # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_count::total 157813 # number of times we switched to this ipl
|
|
system.cpu0.kern.ipl_good::0 62631 49.19% 49.19% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::21 131 0.10% 49.30% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::22 1926 1.51% 50.81% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::30 175 0.14% 50.95% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::31 62456 49.05% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_good::total 127319 # number of times we switched to this ipl from a different ipl
|
|
system.cpu0.kern.ipl_ticks::0 1863112245000 97.74% 97.74% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::21 65536000 0.00% 97.74% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::22 577434000 0.03% 97.77% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::30 84972500 0.00% 97.78% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::31 42413276000 2.22% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_ticks::total 1906253463500 # number of cycles we spent at this ipl
|
|
system.cpu0.kern.ipl_used::0 0.983836 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::31 0.679453 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.ipl_used::total 0.806771 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu0.kern.syscall::2 7 3.93% 3.93% # number of syscalls executed
|
|
system.cpu0.kern.syscall::3 15 8.43% 12.36% # number of syscalls executed
|
|
system.cpu0.kern.syscall::4 4 2.25% 14.61% # number of syscalls executed
|
|
system.cpu0.kern.syscall::6 26 14.61% 29.21% # number of syscalls executed
|
|
system.cpu0.kern.syscall::12 1 0.56% 29.78% # number of syscalls executed
|
|
system.cpu0.kern.syscall::17 6 3.37% 33.15% # number of syscalls executed
|
|
system.cpu0.kern.syscall::19 7 3.93% 37.08% # number of syscalls executed
|
|
system.cpu0.kern.syscall::20 4 2.25% 39.33% # number of syscalls executed
|
|
system.cpu0.kern.syscall::23 1 0.56% 39.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::24 3 1.69% 41.57% # number of syscalls executed
|
|
system.cpu0.kern.syscall::33 6 3.37% 44.94% # number of syscalls executed
|
|
system.cpu0.kern.syscall::41 2 1.12% 46.07% # number of syscalls executed
|
|
system.cpu0.kern.syscall::45 29 16.29% 62.36% # number of syscalls executed
|
|
system.cpu0.kern.syscall::47 3 1.69% 64.04% # number of syscalls executed
|
|
system.cpu0.kern.syscall::48 8 4.49% 68.54% # number of syscalls executed
|
|
system.cpu0.kern.syscall::54 8 4.49% 73.03% # number of syscalls executed
|
|
system.cpu0.kern.syscall::59 6 3.37% 76.40% # number of syscalls executed
|
|
system.cpu0.kern.syscall::71 17 9.55% 85.96% # number of syscalls executed
|
|
system.cpu0.kern.syscall::73 3 1.69% 87.64% # number of syscalls executed
|
|
system.cpu0.kern.syscall::74 4 2.25% 89.89% # number of syscalls executed
|
|
system.cpu0.kern.syscall::87 1 0.56% 90.45% # number of syscalls executed
|
|
system.cpu0.kern.syscall::90 2 1.12% 91.57% # number of syscalls executed
|
|
system.cpu0.kern.syscall::92 7 3.93% 95.51% # number of syscalls executed
|
|
system.cpu0.kern.syscall::97 2 1.12% 96.63% # number of syscalls executed
|
|
system.cpu0.kern.syscall::98 2 1.12% 97.75% # number of syscalls executed
|
|
system.cpu0.kern.syscall::132 1 0.56% 98.31% # number of syscalls executed
|
|
system.cpu0.kern.syscall::144 1 0.56% 98.88% # number of syscalls executed
|
|
system.cpu0.kern.syscall::147 2 1.12% 100.00% # number of syscalls executed
|
|
system.cpu0.kern.syscall::total 178 # number of syscalls executed
|
|
system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::wripir 278 0.17% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrmces 1 0.00% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrfen 1 0.00% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.17% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpctx 3399 2.05% 2.22% # number of callpals executed
|
|
system.cpu0.kern.callpal::tbi 48 0.03% 2.25% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrent 7 0.00% 2.26% # number of callpals executed
|
|
system.cpu0.kern.callpal::swpipl 151231 91.28% 93.54% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdps 5900 3.56% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::wrusp 2 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::rdusp 8 0.00% 97.10% # number of callpals executed
|
|
system.cpu0.kern.callpal::whami 2 0.00% 97.11% # number of callpals executed
|
|
system.cpu0.kern.callpal::rti 4349 2.63% 99.73% # number of callpals executed
|
|
system.cpu0.kern.callpal::callsys 315 0.19% 99.92% # number of callpals executed
|
|
system.cpu0.kern.callpal::imb 132 0.08% 100.00% # number of callpals executed
|
|
system.cpu0.kern.callpal::total 165676 # number of callpals executed
|
|
system.cpu0.kern.mode_switch::kernel 6738 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::user 1097 # number of protection mode switches
|
|
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
|
|
system.cpu0.kern.mode_good::kernel 1097
|
|
system.cpu0.kern.mode_good::user 1097
|
|
system.cpu0.kern.mode_good::idle 0
|
|
system.cpu0.kern.mode_switch_good::kernel 0.162808 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_switch_good::total 0.280026 # fraction of useful protection mode switches
|
|
system.cpu0.kern.mode_ticks::kernel 1904214078500 99.91% 99.91% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::user 1672761500 0.09% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
|
|
system.cpu0.kern.swap_context 3400 # number of times the context was actually changed
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 2490 # number of quiesce instructions executed
|
|
system.cpu1.kern.inst.hwrei 60423 # number of hwrei instructions executed
|
|
system.cpu1.kern.ipl_count::0 18641 37.27% 37.27% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::22 1925 3.85% 41.12% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::30 278 0.56% 41.67% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::31 29176 58.33% 100.00% # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_count::total 50020 # number of times we switched to this ipl
|
|
system.cpu1.kern.ipl_good::0 18293 47.50% 47.50% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::22 1925 5.00% 52.50% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::30 278 0.72% 53.22% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::31 18016 46.78% 100.00% # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_good::total 38512 # number of times we switched to this ipl from a different ipl
|
|
system.cpu1.kern.ipl_ticks::0 1873859043000 98.29% 98.29% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::22 564907000 0.03% 98.32% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::30 133677500 0.01% 98.32% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::31 31975089500 1.68% 100.00% # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_ticks::total 1906532717000 # number of cycles we spent at this ipl
|
|
system.cpu1.kern.ipl_used::0 0.981331 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::31 0.617494 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.ipl_used::total 0.769932 # fraction of swpipl calls that actually changed the ipl
|
|
system.cpu1.kern.syscall::2 1 0.68% 0.68% # number of syscalls executed
|
|
system.cpu1.kern.syscall::3 15 10.14% 10.81% # number of syscalls executed
|
|
system.cpu1.kern.syscall::6 16 10.81% 21.62% # number of syscalls executed
|
|
system.cpu1.kern.syscall::15 1 0.68% 22.30% # number of syscalls executed
|
|
system.cpu1.kern.syscall::17 9 6.08% 28.38% # number of syscalls executed
|
|
system.cpu1.kern.syscall::19 3 2.03% 30.41% # number of syscalls executed
|
|
system.cpu1.kern.syscall::20 2 1.35% 31.76% # number of syscalls executed
|
|
system.cpu1.kern.syscall::23 3 2.03% 33.78% # number of syscalls executed
|
|
system.cpu1.kern.syscall::24 3 2.03% 35.81% # number of syscalls executed
|
|
system.cpu1.kern.syscall::33 5 3.38% 39.19% # number of syscalls executed
|
|
system.cpu1.kern.syscall::45 25 16.89% 56.08% # number of syscalls executed
|
|
system.cpu1.kern.syscall::47 3 2.03% 58.11% # number of syscalls executed
|
|
system.cpu1.kern.syscall::48 2 1.35% 59.46% # number of syscalls executed
|
|
system.cpu1.kern.syscall::54 2 1.35% 60.81% # number of syscalls executed
|
|
system.cpu1.kern.syscall::58 1 0.68% 61.49% # number of syscalls executed
|
|
system.cpu1.kern.syscall::59 1 0.68% 62.16% # number of syscalls executed
|
|
system.cpu1.kern.syscall::71 37 25.00% 87.16% # number of syscalls executed
|
|
system.cpu1.kern.syscall::74 12 8.11% 95.27% # number of syscalls executed
|
|
system.cpu1.kern.syscall::90 1 0.68% 95.95% # number of syscalls executed
|
|
system.cpu1.kern.syscall::92 2 1.35% 97.30% # number of syscalls executed
|
|
system.cpu1.kern.syscall::132 3 2.03% 99.32% # number of syscalls executed
|
|
system.cpu1.kern.syscall::144 1 0.68% 100.00% # number of syscalls executed
|
|
system.cpu1.kern.syscall::total 148 # number of syscalls executed
|
|
system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::wripir 175 0.33% 0.34% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpctx 1166 2.23% 2.57% # number of callpals executed
|
|
system.cpu1.kern.callpal::tbi 5 0.01% 2.58% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrent 7 0.01% 2.59% # number of callpals executed
|
|
system.cpu1.kern.callpal::swpipl 44628 85.35% 87.94% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdps 2858 5.47% 93.41% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed
|
|
system.cpu1.kern.callpal::wrusp 5 0.01% 93.42% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdusp 1 0.00% 93.42% # number of callpals executed
|
|
system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed
|
|
system.cpu1.kern.callpal::rti 3189 6.10% 99.52% # number of callpals executed
|
|
system.cpu1.kern.callpal::callsys 200 0.38% 99.91% # number of callpals executed
|
|
system.cpu1.kern.callpal::imb 48 0.09% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed
|
|
system.cpu1.kern.callpal::total 52290 # number of callpals executed
|
|
system.cpu1.kern.mode_switch::kernel 1624 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::user 640 # number of protection mode switches
|
|
system.cpu1.kern.mode_switch::idle 2399 # number of protection mode switches
|
|
system.cpu1.kern.mode_good::kernel 844
|
|
system.cpu1.kern.mode_good::user 640
|
|
system.cpu1.kern.mode_good::idle 204
|
|
system.cpu1.kern.mode_switch_good::kernel 0.519704 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::idle 0.085035 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_switch_good::total 0.361999 # fraction of useful protection mode switches
|
|
system.cpu1.kern.mode_ticks::kernel 4862135000 0.26% 0.26% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::user 1013458000 0.05% 0.31% # number of ticks spent at the given mode
|
|
system.cpu1.kern.mode_ticks::idle 1900657116000 99.69% 100.00% # number of ticks spent at the given mode
|
|
system.cpu1.kern.swap_context 1167 # number of times the context was actually changed
|
|
|
|
---------- End Simulation Statistics ----------
|