675 lines
76 KiB
Text
675 lines
76 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.021030 # Number of seconds simulated
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sim_ticks 21029927000 # Number of ticks simulated
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final_tick 21029927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 262496 # Simulator instruction rate (inst/s)
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host_op_rate 262496 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 69357396 # Simulator tick rate (ticks/s)
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host_mem_usage 228212 # Number of bytes of host memory used
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host_seconds 303.21 # Real time elapsed on the host
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sim_insts 79591756 # Number of instructions simulated
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sim_ops 79591756 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu.inst 558848 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 10293248 # Number of bytes read from this memory
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system.physmem.bytes_read::total 10852096 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 558848 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 558848 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 7426112 # Number of bytes written to this memory
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system.physmem.bytes_written::total 7426112 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 8732 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 160832 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 169564 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 116033 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 116033 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 26573939 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 489457144 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 516031083 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 26573939 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 26573939 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 353121150 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 353121150 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 353121150 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 26573939 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 489457144 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 869152232 # Total bandwidth to/from this memory (bytes/s)
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system.cpu.dtb.fetch_hits 0 # ITB hits
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system.cpu.dtb.fetch_misses 0 # ITB misses
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system.cpu.dtb.fetch_acv 0 # ITB acv
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system.cpu.dtb.fetch_accesses 0 # ITB accesses
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system.cpu.dtb.read_hits 22489459 # DTB read hits
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system.cpu.dtb.read_misses 217588 # DTB read misses
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system.cpu.dtb.read_acv 44 # DTB read access violations
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system.cpu.dtb.read_accesses 22707047 # DTB read accesses
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system.cpu.dtb.write_hits 15786869 # DTB write hits
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system.cpu.dtb.write_misses 41269 # DTB write misses
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system.cpu.dtb.write_acv 0 # DTB write access violations
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system.cpu.dtb.write_accesses 15828138 # DTB write accesses
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system.cpu.dtb.data_hits 38276328 # DTB hits
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system.cpu.dtb.data_misses 258857 # DTB misses
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system.cpu.dtb.data_acv 44 # DTB access violations
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system.cpu.dtb.data_accesses 38535185 # DTB accesses
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system.cpu.itb.fetch_hits 14133999 # ITB hits
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system.cpu.itb.fetch_misses 38583 # ITB misses
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system.cpu.itb.fetch_acv 0 # ITB acv
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system.cpu.itb.fetch_accesses 14172582 # ITB accesses
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system.cpu.itb.read_hits 0 # DTB read hits
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system.cpu.itb.read_misses 0 # DTB read misses
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system.cpu.itb.read_acv 0 # DTB read access violations
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system.cpu.itb.read_accesses 0 # DTB read accesses
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.itb.write_acv 0 # DTB write access violations
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system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.itb.data_hits 0 # DTB hits
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system.cpu.itb.data_misses 0 # DTB misses
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system.cpu.itb.data_acv 0 # DTB access violations
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system.cpu.itb.data_accesses 0 # DTB accesses
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system.cpu.workload.num_syscalls 4583 # Number of system calls
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system.cpu.numCycles 42059856 # number of cpu cycles simulated
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.BPredUnit.lookups 16727417 # Number of BP lookups
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system.cpu.BPredUnit.condPredicted 10795081 # Number of conditional branches predicted
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system.cpu.BPredUnit.condIncorrect 475795 # Number of conditional branches incorrect
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system.cpu.BPredUnit.BTBLookups 12310974 # Number of BTB lookups
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system.cpu.BPredUnit.BTBHits 7475407 # Number of BTB hits
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system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu.BPredUnit.usedRAS 1997632 # Number of times the RAS was used to get a target.
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system.cpu.BPredUnit.RASInCorrect 44950 # Number of incorrect RAS predictions.
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system.cpu.fetch.icacheStallCycles 15195386 # Number of cycles fetch is stalled on an Icache miss
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system.cpu.fetch.Insts 106731428 # Number of instructions fetch has processed
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system.cpu.fetch.Branches 16727417 # Number of branches that fetch encountered
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system.cpu.fetch.predictedBranches 9473039 # Number of branches that fetch has predicted taken
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system.cpu.fetch.Cycles 19807941 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu.fetch.SquashCycles 2142694 # Number of cycles fetch has spent squashing
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system.cpu.fetch.BlockedCycles 4831440 # Number of cycles fetch has spent blocked
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system.cpu.fetch.MiscStallCycles 7974 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu.fetch.PendingTrapStallCycles 318425 # Number of stall cycles due to pending traps
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system.cpu.fetch.CacheLines 14133999 # Number of cache lines fetched
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system.cpu.fetch.IcacheSquashes 219929 # Number of outstanding Icache misses that were squashed
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system.cpu.fetch.rateDist::samples 41712717 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::mean 2.558726 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::stdev 3.170110 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::0 21904776 52.51% 52.51% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::1 1546832 3.71% 56.22% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::2 1409518 3.38% 59.60% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::3 1517307 3.64% 63.24% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::4 4200862 10.07% 73.31% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::5 1863663 4.47% 77.78% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::6 687442 1.65% 79.43% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::7 1091312 2.62% 82.04% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::8 7491005 17.96% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.rateDist::total 41712717 # Number of instructions fetched each cycle (Total)
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system.cpu.fetch.branchRate 0.397705 # Number of branch fetches per cycle
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system.cpu.fetch.rate 2.537608 # Number of inst fetches per cycle
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system.cpu.decode.IdleCycles 16282600 # Number of cycles decode is idle
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system.cpu.decode.BlockedCycles 4400388 # Number of cycles decode is blocked
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system.cpu.decode.RunCycles 18871589 # Number of cycles decode is running
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system.cpu.decode.UnblockCycles 713555 # Number of cycles decode is unblocking
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system.cpu.decode.SquashCycles 1444585 # Number of cycles decode is squashing
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system.cpu.decode.BranchResolved 3801857 # Number of times decode resolved a branch
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system.cpu.decode.BranchMispred 109351 # Number of times decode detected a branch misprediction
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system.cpu.decode.DecodedInsts 104838793 # Number of instructions handled by decode
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system.cpu.decode.SquashedInsts 305565 # Number of squashed instructions handled by decode
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system.cpu.rename.SquashCycles 1444585 # Number of cycles rename is squashing
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system.cpu.rename.IdleCycles 16762775 # Number of cycles rename is idle
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system.cpu.rename.BlockCycles 2290284 # Number of cycles rename is blocking
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system.cpu.rename.serializeStallCycles 81927 # count of cycles rename stalled for serializing inst
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system.cpu.rename.RunCycles 19061483 # Number of cycles rename is running
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system.cpu.rename.UnblockCycles 2071663 # Number of cycles rename is unblocking
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system.cpu.rename.RenamedInsts 103408033 # Number of instructions processed by rename
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system.cpu.rename.ROBFullEvents 177 # Number of times rename has blocked due to ROB full
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system.cpu.rename.IQFullEvents 1890 # Number of times rename has blocked due to IQ full
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system.cpu.rename.LSQFullEvents 1956072 # Number of times rename has blocked due to LSQ full
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system.cpu.rename.RenamedOperands 62335498 # Number of destination operands rename has renamed
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system.cpu.rename.RenameLookups 124694291 # Number of register rename lookups that rename has made
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system.cpu.rename.int_rename_lookups 124234000 # Number of integer rename lookups
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system.cpu.rename.fp_rename_lookups 460291 # Number of floating rename lookups
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system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed
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system.cpu.rename.UndoneMaps 9788617 # Number of HB maps that are undone due to squashing
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system.cpu.rename.serializingInsts 5545 # count of serializing insts renamed
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system.cpu.rename.tempSerializingInsts 5542 # count of temporary serializing insts renamed
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system.cpu.rename.skidInsts 4401091 # count of insts added to the skid buffer
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system.cpu.memDep0.insertedLoads 23371275 # Number of loads inserted to the mem dependence unit.
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system.cpu.memDep0.insertedStores 16383320 # Number of stores inserted to the mem dependence unit.
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system.cpu.memDep0.conflictingLoads 1113297 # Number of conflicting loads.
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system.cpu.memDep0.conflictingStores 382577 # Number of conflicting stores.
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system.cpu.iq.iqInstsAdded 91444399 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu.iq.iqNonSpecInstsAdded 5409 # Number of non-speculative instructions added to the IQ
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system.cpu.iq.iqInstsIssued 89052036 # Number of instructions issued
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system.cpu.iq.iqSquashedInstsIssued 123621 # Number of squashed instructions issued
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system.cpu.iq.iqSquashedInstsExamined 11266129 # Number of squashed instructions iterated over during squash; mainly for profiling
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system.cpu.iq.iqSquashedOperandsExamined 4895344 # Number of squashed operands that are examined and possibly removed from graph
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system.cpu.iq.iqSquashedNonSpecRemoved 826 # Number of squashed non-spec instructions that were removed
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system.cpu.iq.issued_per_cycle::samples 41712717 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::mean 2.134889 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::stdev 2.120974 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::0 13445094 32.23% 32.23% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::1 6815105 16.34% 48.57% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::2 5522712 13.24% 61.81% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::3 4804260 11.52% 73.33% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::4 4760133 11.41% 84.74% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::5 2656664 6.37% 91.11% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::6 1952953 4.68% 95.79% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 1309211 3.14% 98.93% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::8 446585 1.07% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::total 41712717 # Number of insts issued each cycle
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system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntAlu 129648 6.83% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntMult 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::IntDiv 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatMult 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMult 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShift 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.83% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemRead 800646 42.16% 48.99% # attempts to use FU when none available
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system.cpu.iq.fu_full::MemWrite 968600 51.01% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
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system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IntAlu 49748943 55.87% 55.87% # Type of FU issued
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system.cpu.iq.FU_type_0::IntMult 43836 0.05% 55.91% # Type of FU issued
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system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.91% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatAdd 121395 0.14% 56.05% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 56.05% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatCvt 122222 0.14% 56.19% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatMult 56 0.00% 56.19% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatDiv 38945 0.04% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.23% # Type of FU issued
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system.cpu.iq.FU_type_0::MemRead 22978145 25.80% 82.03% # Type of FU issued
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system.cpu.iq.FU_type_0::MemWrite 15998405 17.97% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
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system.cpu.iq.FU_type_0::total 89052036 # Type of FU issued
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system.cpu.iq.rate 2.117269 # Inst issue rate
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system.cpu.iq.fu_busy_cnt 1898894 # FU busy when requested
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system.cpu.iq.fu_busy_rate 0.021323 # FU busy rate (busy events/executed inst)
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system.cpu.iq.int_inst_queue_reads 221228638 # Number of integer instruction queue reads
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system.cpu.iq.int_inst_queue_writes 102311745 # Number of integer instruction queue writes
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system.cpu.iq.int_inst_queue_wakeup_accesses 87003241 # Number of integer instruction queue wakeup accesses
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system.cpu.iq.fp_inst_queue_reads 610666 # Number of floating instruction queue reads
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system.cpu.iq.fp_inst_queue_writes 420329 # Number of floating instruction queue writes
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system.cpu.iq.fp_inst_queue_wakeup_accesses 297405 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.int_alu_accesses 90645490 # Number of integer alu accesses
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system.cpu.iq.fp_alu_accesses 305440 # Number of floating point alu accesses
|
|
system.cpu.iew.lsq.thread0.forwLoads 1454782 # Number of loads that had data forwarded from stores
|
|
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.squashedLoads 3094637 # Number of loads squashed
|
|
system.cpu.iew.lsq.thread0.ignoredResponses 5405 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu.iew.lsq.thread0.memOrderViolation 17198 # Number of memory ordering violations
|
|
system.cpu.iew.lsq.thread0.squashedStores 1769943 # Number of stores squashed
|
|
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu.iew.lsq.thread0.rescheduledLoads 2465 # Number of loads that were rescheduled
|
|
system.cpu.iew.lsq.thread0.cacheBlocked 56 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu.iew.iewSquashCycles 1444585 # Number of cycles IEW is squashing
|
|
system.cpu.iew.iewBlockCycles 1378750 # Number of cycles IEW is blocking
|
|
system.cpu.iew.iewUnblockCycles 59667 # Number of cycles IEW is unblocking
|
|
system.cpu.iew.iewDispatchedInsts 100988081 # Number of instructions dispatched to IQ
|
|
system.cpu.iew.iewDispSquashedInsts 245674 # Number of squashed instructions skipped by dispatch
|
|
system.cpu.iew.iewDispLoadInsts 23371275 # Number of dispatched load instructions
|
|
system.cpu.iew.iewDispStoreInsts 16383320 # Number of dispatched store instructions
|
|
system.cpu.iew.iewDispNonSpecInsts 5409 # Number of dispatched non-speculative instructions
|
|
system.cpu.iew.iewIQFullEvents 41936 # Number of times the IQ has become full, causing a stall
|
|
system.cpu.iew.iewLSQFullEvents 387 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu.iew.memOrderViolationEvents 17198 # Number of memory order violations
|
|
system.cpu.iew.predictedTakenIncorrect 251719 # Number of branches that were predicted taken incorrectly
|
|
system.cpu.iew.predictedNotTakenIncorrect 174529 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu.iew.branchMispredicts 426248 # Number of branch mispredicts detected at execute
|
|
system.cpu.iew.iewExecutedInsts 88078074 # Number of executed instructions
|
|
system.cpu.iew.iewExecLoadInsts 22710515 # Number of load instructions executed
|
|
system.cpu.iew.iewExecSquashedInsts 973962 # Number of squashed instructions skipped in execute
|
|
system.cpu.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu.iew.exec_nop 9538273 # number of nop insts executed
|
|
system.cpu.iew.exec_refs 38539046 # number of memory reference insts executed
|
|
system.cpu.iew.exec_branches 15143390 # Number of branches executed
|
|
system.cpu.iew.exec_stores 15828531 # Number of stores executed
|
|
system.cpu.iew.exec_rate 2.094113 # Inst execution rate
|
|
system.cpu.iew.wb_sent 87713914 # cumulative count of insts sent to commit
|
|
system.cpu.iew.wb_count 87300646 # cumulative count of insts written-back
|
|
system.cpu.iew.wb_producers 33458604 # num instructions producing a value
|
|
system.cpu.iew.wb_consumers 43597958 # num instructions consuming a value
|
|
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu.iew.wb_rate 2.075629 # insts written-back per cycle
|
|
system.cpu.iew.wb_fanout 0.767435 # average fanout of values written-back
|
|
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions
|
|
system.cpu.commit.commitCommittedOps 88340672 # The number of committed instructions
|
|
system.cpu.commit.commitSquashedInsts 9531604 # The number of squashed insts skipped by commit
|
|
system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu.commit.branchMispredicts 368829 # The number of times a branch was mispredicted
|
|
system.cpu.commit.committed_per_cycle::samples 40268132 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::mean 2.193811 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::stdev 2.828127 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::0 17348502 43.08% 43.08% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::1 7047839 17.50% 60.58% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::2 3405424 8.46% 69.04% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::3 2108778 5.24% 74.28% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::4 2046687 5.08% 79.36% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::5 1183274 2.94% 82.30% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::6 1130602 2.81% 85.11% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::7 707287 1.76% 86.86% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::8 5289739 13.14% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu.commit.committed_per_cycle::total 40268132 # Number of insts commited each cycle
|
|
system.cpu.commit.committedInsts 88340672 # Number of instructions committed
|
|
system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed
|
|
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu.commit.refs 34890015 # Number of memory references committed
|
|
system.cpu.commit.loads 20276638 # Number of loads committed
|
|
system.cpu.commit.membars 0 # Number of memory barriers committed
|
|
system.cpu.commit.branches 13754477 # Number of branches committed
|
|
system.cpu.commit.fp_insts 267754 # Number of committed floating point instructions.
|
|
system.cpu.commit.int_insts 77942044 # Number of committed integer instructions.
|
|
system.cpu.commit.function_calls 1661057 # Number of function calls committed.
|
|
system.cpu.commit.bw_lim_events 5289739 # number cycles where commit BW limit reached
|
|
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu.rob.rob_reads 131533327 # The number of ROB reads
|
|
system.cpu.rob.rob_writes 197192647 # The number of ROB writes
|
|
system.cpu.timesIdled 15699 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu.idleCycles 347139 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
|
|
system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated
|
|
system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
|
|
system.cpu.cpi 0.528445 # CPI: Cycles Per Instruction
|
|
system.cpu.cpi_total 0.528445 # CPI: Total CPI of All Threads
|
|
system.cpu.ipc 1.892345 # IPC: Instructions Per Cycle
|
|
system.cpu.ipc_total 1.892345 # IPC: Total IPC of All Threads
|
|
system.cpu.int_regfile_reads 116616744 # number of integer regfile reads
|
|
system.cpu.int_regfile_writes 57879304 # number of integer regfile writes
|
|
system.cpu.fp_regfile_reads 252339 # number of floating regfile reads
|
|
system.cpu.fp_regfile_writes 241658 # number of floating regfile writes
|
|
system.cpu.misc_regfile_reads 38301 # number of misc regfile reads
|
|
system.cpu.misc_regfile_writes 1 # number of misc regfile writes
|
|
system.cpu.icache.replacements 93371 # number of replacements
|
|
system.cpu.icache.tagsinuse 1930.973067 # Cycle average of tags in use
|
|
system.cpu.icache.total_refs 14034495 # Total number of references to valid blocks.
|
|
system.cpu.icache.sampled_refs 95419 # Sample count of references to valid blocks.
|
|
system.cpu.icache.avg_refs 147.082814 # Average number of references to valid blocks.
|
|
system.cpu.icache.warmup_cycle 17612659000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.occ_blocks::cpu.inst 1930.973067 # Average occupied blocks per requestor
|
|
system.cpu.icache.occ_percent::cpu.inst 0.942858 # Average percentage of cache occupancy
|
|
system.cpu.icache.occ_percent::total 0.942858 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 14034495 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 14034495 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 14034495 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 14034495 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 14034495 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 14034495 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 99504 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 99504 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 99504 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 99504 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 99504 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 99504 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 887461000 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 887461000 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 887461000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 887461000 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 887461000 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 887461000 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 14133999 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 14133999 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 14133999 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 14133999 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 14133999 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 14133999 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007040 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.007040 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.007040 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.007040 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.007040 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.007040 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8918.847484 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 8918.847484 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 8918.847484 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 8918.847484 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 8918.847484 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 8918.847484 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4084 # number of ReadReq MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_hits::total 4084 # number of ReadReq MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::cpu.inst 4084 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.demand_mshr_hits::total 4084 # number of demand (read+write) MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::cpu.inst 4084 # number of overall MSHR hits
|
|
system.cpu.icache.overall_mshr_hits::total 4084 # number of overall MSHR hits
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95420 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 95420 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 95420 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 95420 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 95420 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 95420 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 511334500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 511334500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 511334500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 511334500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 511334500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 511334500 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006751 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.006751 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006751 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.006751 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 5358.776986 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 5358.776986 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 5358.776986 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 5358.776986 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.replacements 201494 # number of replacements
|
|
system.cpu.dcache.tagsinuse 4076.242085 # Cycle average of tags in use
|
|
system.cpu.dcache.total_refs 34356241 # Total number of references to valid blocks.
|
|
system.cpu.dcache.sampled_refs 205590 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.avg_refs 167.110467 # Average number of references to valid blocks.
|
|
system.cpu.dcache.warmup_cycle 156434000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.occ_blocks::cpu.data 4076.242085 # Average occupied blocks per requestor
|
|
system.cpu.dcache.occ_percent::cpu.data 0.995176 # Average percentage of cache occupancy
|
|
system.cpu.dcache.occ_percent::total 0.995176 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 20778024 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 20778024 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 13578147 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 13578147 # number of WriteReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 70 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 70 # number of LoadLockedReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 34356171 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 34356171 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 34356171 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 34356171 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 254081 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 254081 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 1035230 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 1035230 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1289311 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1289311 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1289311 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1289311 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7948579000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 7948579000 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 34030906498 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 34030906498 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 41979485498 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 41979485498 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 41979485498 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 41979485498 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 21032105 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 21032105 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 70 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 70 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 35645482 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 35645482 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 35645482 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 35645482 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012081 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.012081 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.070841 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.070841 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.036170 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.036170 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.036170 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.036170 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31283.641831 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 31283.641831 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32872.797830 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 32872.797830 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 32559.627195 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 32559.627195 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 32559.627195 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 100500 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs 5911.764706 # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 166286 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 166286 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 191915 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 191915 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 891806 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 891806 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 1083721 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 1083721 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 1083721 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 1083721 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62166 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 62166 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143424 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 143424 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 205590 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 205590 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 205590 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 205590 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1142650000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 1142650000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4721135000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 4721135000 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5863785000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 5863785000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5863785000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 5863785000 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002956 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002956 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009815 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009815 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005768 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.005768 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005768 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.005768 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18380.626066 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18380.626066 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32917.329038 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32917.329038 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28521.742303 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 28521.742303 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28521.742303 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 28521.742303 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.replacements 137157 # number of replacements
|
|
system.cpu.l2cache.tagsinuse 29150.308284 # Cycle average of tags in use
|
|
system.cpu.l2cache.total_refs 155579 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.sampled_refs 168030 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.avg_refs 0.925900 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.occ_blocks::writebacks 25379.974502 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.inst 1916.859149 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_blocks::cpu.data 1853.474632 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.occ_percent::writebacks 0.774535 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.inst 0.058498 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::cpu.data 0.056564 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.occ_percent::total 0.889597 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 86688 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 32293 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 118981 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 166286 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 166286 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 12465 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 12465 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 86688 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 44758 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 131446 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 86688 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 44758 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 131446 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 8732 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 29871 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 38603 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 130961 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 130961 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 8732 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 160832 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 169564 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 8732 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 160832 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 169564 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 299903500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1029755500 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 1329659000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4515967000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 4515967000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 299903500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 5545722500 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 5845626000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 299903500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 5545722500 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 5845626000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 95420 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 62164 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 157584 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 166286 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 166286 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143426 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 143426 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 95420 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 205590 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 301010 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 95420 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 205590 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 301010 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.091511 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.480519 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.244968 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.913091 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.913091 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.091511 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.782295 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.563317 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.091511 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.782295 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.563317 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34345.338983 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34473.419035 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 34444.447323 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34483.296554 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34483.296554 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34345.338983 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34481.462022 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 34474.452124 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34345.338983 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34481.462022 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 34474.452124 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 28000 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2545.454545 # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 116033 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 116033 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8732 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 29871 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 38603 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130961 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 130961 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 8732 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 160832 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 169564 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 8732 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 160832 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 169564 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 271655000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 927105000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1198760000 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4112324500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4112324500 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 271655000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5039429500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 5311084500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 271655000 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5039429500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 5311084500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.480519 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.244968 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.913091 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.913091 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.782295 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.563317 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.091511 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.782295 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.563317 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31110.284013 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31036.958923 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31053.545061 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31401.138507 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31401.138507 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31110.284013 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31333.500174 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31322.005261 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31110.284013 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31333.500174 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31322.005261 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|