309e1d8193
TimingSimpleCPU, which use atomic and timing memory accesses respectively. Common code is factored into the BaseSimpleCPU class. AtomicSimpleCPU includes an option (simulate_stalls) to add delays based on the estimated latency reported by the atomic accesses. Plain old "SimpleCPU" is gone; I have not updated all the config files (just test/test.py). Also fixes to get timing accesses working in new memory model and to get split-phase memory instruction definitions working with new memory model as well. arch/alpha/isa/main.isa: Need to include packet_impl.h for functions that use Packet objects. arch/alpha/isa/mem.isa: Change completeAcc() methods to take Packet object pointers. Also split out StoreCond template for completeAcc(), since that's the only one that needs write_result and we get an unused variable warning if we always have it in there. build/SConstruct: Update list of recognized CPU model names. configs/test/test.py: Change SimpleCPU to AtomicSimpleCPU. cpu/SConscript: Define sources for new CPU models. Add split memory access methods to CPU model signatures. cpu/cpu_models.py: cpu/static_inst.hh: Define new CPU models. cpu/simple/base.cc: cpu/simple/base.hh: Factor out pieces specific to Atomic or Timing models. mem/bus.cc: Bus needs to be able to route timing packets based on explicit dest so responses can get back to requester. Set dest to Packet::Broadcast to indicate that dest should be derived from address. Also set packet src field based on port from which packet is sent. mem/bus.hh: Set packet src field based on port from which packet is sent. mem/packet.hh: Define Broadcast destination address to indicate that packet should be routed based on address. mem/physical.cc: Set packet dest on response so packet is routed back to requester properly. mem/port.cc: Flag blob packets as Broadcast. python/m5/objects/PhysicalMemory.py: Change default latency to be 1 cycle. --HG-- rename : cpu/simple/cpu.cc => cpu/simple/base.cc rename : cpu/simple/cpu.hh => cpu/simple/base.hh extra : convert_revision : e9646af6406a20c8c605087936dc4683375c2132
188 lines
5.7 KiB
C++
188 lines
5.7 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file Definition of a bus object.
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*/
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#include "base/trace.hh"
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#include "mem/bus.hh"
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#include "sim/builder.hh"
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/** Get the ranges of anyone that we are connected to. */
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void
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Bus::init()
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{
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std::vector<Port*>::iterator intIter;
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for (intIter = interfaces.begin(); intIter != interfaces.end(); intIter++)
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(*intIter)->sendStatusChange(Port::RangeChange);
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}
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/** Function called by the port when the bus is recieving a Timing
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* transaction.*/
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bool
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Bus::recvTiming(Packet &pkt)
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{
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Port *port;
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if (pkt.dest == Packet::Broadcast) {
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port = findPort(pkt.addr, pkt.src);
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} else {
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assert(pkt.dest > 0 && pkt.dest < interfaces.size());
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port = interfaces[pkt.dest];
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}
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return port->sendTiming(pkt);
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}
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Port *
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Bus::findPort(Addr addr, int id)
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{
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/* An interval tree would be a better way to do this. --ali. */
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int dest_id = -1;
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int i = 0;
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bool found = false;
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while (i < portList.size() && !found)
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{
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if (portList[i].range == addr) {
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dest_id = portList[i].portId;
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found = true;
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DPRINTF(Bus, "Found Addr: %llx on device %d\n", addr, dest_id);
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}
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i++;
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}
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if (dest_id == -1)
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panic("Unable to find destination for addr: %llx", addr);
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// we shouldn't be sending this back to where it came from
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assert(dest_id != id);
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return interfaces[dest_id];
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}
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/** Function called by the port when the bus is recieving a Atomic
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* transaction.*/
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Tick
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Bus::recvAtomic(Packet &pkt)
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{
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assert(pkt.dest == Packet::Broadcast);
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return findPort(pkt.addr, pkt.src)->sendAtomic(pkt);
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}
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/** Function called by the port when the bus is recieving a Functional
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* transaction.*/
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void
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Bus::recvFunctional(Packet &pkt)
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{
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assert(pkt.dest == Packet::Broadcast);
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findPort(pkt.addr, pkt.src)->sendFunctional(pkt);
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}
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/** Function called by the port when the bus is recieving a status change.*/
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void
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Bus::recvStatusChange(Port::Status status, int id)
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{
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DPRINTF(Bus, "Bus %d recieved status change from device id %d\n",
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busId, id);
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assert(status == Port::RangeChange &&
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"The other statuses need to be implemented.");
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assert(id < interfaces.size() && id >= 0);
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int x;
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Port *port = interfaces[id];
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AddrRangeList ranges;
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AddrRangeList snoops;
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AddrRangeIter iter;
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std::vector<DevMap>::iterator portIter;
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// Clean out any previously existent ids
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for (portIter = portList.begin(); portIter != portList.end(); ) {
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if (portIter->portId == id)
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portIter = portList.erase(portIter);
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else
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portIter++;
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}
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port->getPeerAddressRanges(ranges, snoops);
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// not dealing with snooping yet either
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assert(snoops.size() == 0);
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for(iter = ranges.begin(); iter != ranges.end(); iter++) {
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DevMap dm;
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dm.portId = id;
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dm.range = *iter;
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DPRINTF(MMU, "Adding range %llx - %llx for id %d\n", dm.range.start,
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dm.range.end, id);
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portList.push_back(dm);
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}
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DPRINTF(MMU, "port list has %d entries\n", portList.size());
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// tell all our peers that our address range has changed.
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// Don't tell the device that caused this change, it already knows
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for (x = 0; x < interfaces.size(); x++)
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if (x != id)
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interfaces[x]->sendStatusChange(Port::RangeChange);
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}
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void
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Bus::addressRanges(AddrRangeList &resp, AddrRangeList &snoop, int id)
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{
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std::vector<DevMap>::iterator portIter;
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resp.clear();
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snoop.clear();
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DPRINTF(Bus, "Bus id %d recieved address range request returning\n",
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busId);
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for (portIter = portList.begin(); portIter != portList.end(); portIter++) {
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if (portIter->portId != id) {
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resp.push_back(portIter->range);
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DPRINTF(Bus, "-- %#llX : %#llX\n", portIter->range.start,
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portIter->range.end);
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}
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}
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(Bus)
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Param<int> bus_id;
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END_DECLARE_SIM_OBJECT_PARAMS(Bus)
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BEGIN_INIT_SIM_OBJECT_PARAMS(Bus)
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INIT_PARAM(bus_id, "a globally unique bus id")
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END_INIT_SIM_OBJECT_PARAMS(Bus)
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CREATE_SIM_OBJECT(Bus)
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{
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return new Bus(getInstanceName(), bus_id);
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}
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REGISTER_SIM_OBJECT("Bus", Bus)
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