d3ed32b989
In Linux, the set_thread_area system call stores the address of the thread local storage area into a field of the current thread_info structure. Later, to access that value, the program uses the rdhwr instruction to read a "hardware register" with index 29. The 64 bit MIPS manual, volume II, says that index 29 is reserved for a future ABI extension and should cause a "Reserved Instruction Exception". In Linux (and potentially other ISAs) that exception is trapped and emulated to return the value stored by set_thread_area as if that were actually stored by a physical register. The tp_value address (as named in the Linux kernel) is ironically stored as a control register so that it goes with a particular ThreadContext. Syscall emulation will use that to emulate storing to the OS's thread info structure, and rdhwr will emulate faulting and returning that value from software by returning the value itself, as if it was in hardware. In other words, we fake faking the register in SE mode. In an FS mode implementation it should work as specified in the manual.
156 lines
6.9 KiB
C++
156 lines
6.9 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2007 MIPS Technologies, Inc.
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Korey Sewell
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// Jaidev Patwardhan
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def operand_types {{
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'sb' : ('signed int', 8),
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'ub' : ('unsigned int', 8),
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'sh' : ('signed int', 16),
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'uh' : ('unsigned int', 16),
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'sw' : ('signed int', 32),
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'uw' : ('unsigned int', 32),
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'sd' : ('signed int', 64),
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'ud' : ('unsigned int', 64),
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'sf' : ('float', 32),
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'df' : ('float', 64),
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}};
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def operands {{
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#General Purpose Integer Reg Operands
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'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
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'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2),
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'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 3),
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#Immediate Value operand
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'IntImm': ('IntReg', 'uw', 'INTIMM', 'IsInteger', 3),
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#Operands used for Link or Syscall Insts
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'R31': ('IntReg', 'uw','31','IsInteger', 4),
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'R2': ('IntReg', 'uw','2', 'IsInteger', 5),
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#Special Integer Reg operands
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'LO0': ('IntReg', 'uw','INTREG_LO', 'IsInteger', 6),
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'HI0': ('IntReg', 'uw','INTREG_HI', 'IsInteger', 7),
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#Bitfield-dependent HI/LO Register Access
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'LO_RD_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACDST*3', None, 6),
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'HI_RD_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACDST*3', None, 7),
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'LO_RS_SEL': ('IntReg','uw','INTREG_DSP_LO0 + ACSRC*3', None, 6),
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'HI_RS_SEL': ('IntReg','uw','INTREG_DSP_HI0 + ACSRC*3', None, 7),
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#DSP Special Purpose Integer Operands
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'DSPControl': ('IntReg', 'uw', 'INTREG_DSP_CONTROL', None, 8),
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'DSPLo0': ('IntReg', 'uw', 'INTREG_LO', None, 1),
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'DSPHi0': ('IntReg', 'uw', 'INTREG_HI', None, 1),
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'DSPACX0': ('IntReg', 'uw', 'INTREG_DSP_ACX0', None, 1),
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'DSPLo1': ('IntReg', 'uw', 'INTREG_DSP_LO1', None, 1),
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'DSPHi1': ('IntReg', 'uw', 'INTREG_DSP_HI1', None, 1),
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'DSPACX1': ('IntReg', 'uw', 'INTREG_DSP_ACX1', None, 1),
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'DSPLo2': ('IntReg', 'uw', 'INTREG_DSP_LO2', None, 1),
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'DSPHi2': ('IntReg', 'uw', 'INTREG_DSP_HI2', None, 1),
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'DSPACX2': ('IntReg', 'uw', 'INTREG_DSP_ACX2', None, 1),
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'DSPLo3': ('IntReg', 'uw', 'INTREG_DSP_LO3', None, 1),
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'DSPHi3': ('IntReg', 'uw', 'INTREG_DSP_HI3', None, 1),
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'DSPACX3': ('IntReg', 'uw', 'INTREG_DSP_ACX3', None, 1),
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#Floating Point Reg Operands
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'Fd': ('FloatReg', 'sf', 'FD', 'IsFloating', 1),
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'Fs': ('FloatReg', 'sf', 'FS', 'IsFloating', 2),
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'Ft': ('FloatReg', 'sf', 'FT', 'IsFloating', 3),
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'Fr': ('FloatReg', 'sf', 'FR', 'IsFloating', 3),
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#Special Purpose Floating Point Control Reg Operands
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'FIR': ('FloatReg', 'uw', 'FLOATREG_FIR', 'IsFloating', 1),
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'FCCR': ('FloatReg', 'uw', 'FLOATREG_FCCR', 'IsFloating', 2),
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'FEXR': ('FloatReg', 'uw', 'FLOATREG_FEXR', 'IsFloating', 3),
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'FENR': ('FloatReg', 'uw', 'FLOATREG_FENR', 'IsFloating', 3),
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'FCSR': ('FloatReg', 'uw', 'FLOATREG_FCSR', 'IsFloating', 3),
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#Operands For Paired Singles FP Operations
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'Fd1': ('FloatReg', 'sf', 'FD', 'IsFloating', 4),
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'Fd2': ('FloatReg', 'sf', 'FD+1', 'IsFloating', 4),
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'Fs1': ('FloatReg', 'sf', 'FS', 'IsFloating', 5),
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'Fs2': ('FloatReg', 'sf', 'FS+1', 'IsFloating', 5),
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'Ft1': ('FloatReg', 'sf', 'FT', 'IsFloating', 6),
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'Ft2': ('FloatReg', 'sf', 'FT+1', 'IsFloating', 6),
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'Fr1': ('FloatReg', 'sf', 'FR', 'IsFloating', 7),
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'Fr2': ('FloatReg', 'sf', 'FR+1', 'IsFloating', 7),
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#Status Control Reg
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'Status': ('ControlReg', 'uw', 'MISCREG_STATUS', None, 1),
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#LL Flag
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'LLFlag': ('ControlReg', 'uw', 'MISCREG_LLFLAG', None, 1),
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#Thread pointer value for SE mode
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'TpValue': ('ControlReg', 'ud', 'MISCREG_TP_VALUE', None, 1),
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# Index Register
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'Index': ('ControlReg','uw','MISCREG_INDEX',None,1),
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'CP0_RD_SEL': ('ControlReg', 'uw', '(RD << 3 | SEL)', None, 1),
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#MT Control Regs
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'MVPConf0': ('ControlReg', 'uw', 'MISCREG_MVP_CONF0', None, 1),
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'MVPControl': ('ControlReg', 'uw', 'MISCREG_MVP_CONTROL', None, 1),
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'TCBind': ('ControlReg', 'uw', 'MISCREG_TC_BIND', None, 1),
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'TCStatus': ('ControlReg', 'uw', 'MISCREG_TC_STATUS', None, 1),
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'TCRestart': ('ControlReg', 'uw', 'MISCREG_TC_RESTART', None, 1),
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'VPEConf0': ('ControlReg', 'uw', 'MISCREG_VPE_CONF0', None, 1),
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'VPEControl': ('ControlReg', 'uw', 'MISCREG_VPE_CONTROL', None, 1),
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'YQMask': ('ControlReg', 'uw', 'MISCREG_YQMASK', None, 1),
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#CP0 Control Regs
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'EntryHi': ('ControlReg','uw', 'MISCREG_ENTRYHI',None,1),
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'EntryLo0': ('ControlReg','uw', 'MISCREG_ENTRYLO0',None,1),
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'EntryLo1': ('ControlReg','uw', 'MISCREG_ENTRYLO1',None,1),
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'PageMask': ('ControlReg','uw', 'MISCREG_PAGEMASK',None,1),
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'Random': ('ControlReg','uw', 'MISCREG_CP0_RANDOM',None,1),
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'ErrorEPC': ('ControlReg','uw', 'MISCREG_ERROR_EPC',None,1),
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'EPC': ('ControlReg','uw', 'MISCREG_EPC',None,1),
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'DEPC': ('ControlReg','uw', 'MISCREG_DEPC',None,1),
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'IntCtl': ('ControlReg','uw', 'MISCREG_INTCTL',None,1),
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'SRSCtl': ('ControlReg','uw', 'MISCREG_SRSCTL',None,1),
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'Config': ('ControlReg','uw', 'MISCREG_CONFIG',None,1),
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'Config3': ('ControlReg','uw', 'MISCREG_CONFIG3',None,1),
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'Config1': ('ControlReg','uw', 'MISCREG_CONFIG1',None,1),
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'Config2': ('ControlReg','uw', 'MISCREG_CONFIG2',None,1),
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'PageGrain': ('ControlReg','uw', 'MISCREG_PAGEGRAIN',None,1),
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'Debug': ('ControlReg','uw', 'MISCREG_DEBUG',None,1),
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'Cause': ('ControlReg','uw', 'MISCREG_CAUSE',None,1),
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#Memory Operand
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'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
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#Program Counter Operands
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'NPC': ('NPC', 'uw', None, 'IsControl', 4),
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'NNPC':('NNPC', 'uw', None, 'IsControl', 4)
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}};
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