gem5/src
Andreas Hansson 36dc93a5fa mem: Move crossbar default latencies to subclasses
This patch introduces a few subclasses to the CoherentXBar and
NoncoherentXBar to distinguish the different uses in the system. We
use the crossbar in a wide range of places: interfacing cores to the
L2, as a system interconnect, connecting I/O and peripherals,
etc. Needless to say, these crossbars have very different performance,
and the clock frequency alone is not enough to distinguish these
scenarios.

Instead of trying to capture every possible case, this patch
introduces dedicated subclasses for the three primary use-cases:
L2XBar, SystemXBar and IOXbar. More can be added if needed, and the
defaults can be overridden.
2015-03-02 04:00:47 -05:00
..
arch arm: Share a port for the two table walker objects 2015-03-02 04:00:42 -05:00
base base: Add compiler macros to add deprecation warnings 2015-02-11 10:23:24 -05:00
cpu mem: Move crossbar default latencies to subclasses 2015-03-02 04:00:47 -05:00
dev dev, arm: Clean up PL011 and rewrite interrupt handling 2015-03-02 04:00:44 -05:00
doc cpu: `Minor' in-order CPU model 2014-07-23 16:09:04 -05:00
doxygen MEM: Put memory system document into doxygen 2012-09-25 11:49:41 -05:00
kern misc: Move AddrRangeList from port.hh to addr_range.hh 2014-10-16 05:49:59 -04:00
mem mem: Move crossbar default latencies to subclasses 2015-03-02 04:00:47 -05:00
proto cpu: add support for outputing a protobuf formatted CPU trace 2015-02-16 03:32:38 -05:00
python base: Add XOR-based hashed address interleaving 2015-02-03 14:25:54 -05:00
sim mem: Split port retry for all different packet classes 2015-03-02 04:00:35 -05:00
unittest test: Add a unittest for the BitUnion types. 2015-01-07 00:34:40 -08:00
Doxyfile Doxygen: Update the version of the Doxyfile 2012-10-11 06:38:42 -04:00
SConscript base: Add compiler macros to add deprecation warnings 2015-02-11 10:23:24 -05:00