Andreas Hansson 368f50a0a1 mem: Cycles converted to Ticks in atomic cache accesses ... This patch fixes an outstanding issue in the cache timing calculations where an atomic access returned a time in Cycles, but the port forwarded it on as if it was in Ticks. A separate patch will update the regression stats.		2013-06-27 05:49:49 -04:00
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prefetch	mem: Add deferred packet class to prefetcher	2013-02-19 05:56:06 -05:00
tags	mem: Adding verbose debug output in the memory system	2013-04-22 13:20:33 -04:00
base.cc	mem: Cancel cache retry event when blocking port	2013-03-26 14:46:51 -04:00
base.hh	mem: Tighten up cache constness and scoping	2013-02-15 17:40:10 -05:00
BaseCache.py	mem: Remove the IIC replacement policy	2013-01-07 13:05:39 -05:00
blk.cc	Fix #include lines for renamed cache files.	2008-02-10 14:45:25 -08:00
blk.hh	mem: Adding verbose debug output in the memory system	2013-04-22 13:20:33 -04:00
builder.cc	mem: Remove the IIC replacement policy	2013-01-07 13:05:39 -05:00
cache.cc	mem: Remove the IIC replacement policy	2013-01-07 13:05:39 -05:00
cache.hh	mem: Cycles converted to Ticks in atomic cache accesses	2013-06-27 05:49:49 -04:00
cache_impl.hh	mem: Cycles converted to Ticks in atomic cache accesses	2013-06-27 05:49:49 -04:00
mshr.cc	mem: Spring cleaning of MSHR and MSHRQueue	2013-05-30 12:54:11 -04:00
mshr.hh	mem: Spring cleaning of MSHR and MSHRQueue	2013-05-30 12:54:11 -04:00
mshr_queue.cc	mem: Spring cleaning of MSHR and MSHRQueue	2013-05-30 12:54:11 -04:00
mshr_queue.hh	mem: Spring cleaning of MSHR and MSHRQueue	2013-05-30 12:54:11 -04:00
SConscript	mem: Adding verbose debug output in the memory system	2013-04-22 13:20:33 -04:00