a62afd094b
This patch fixes the warnings that clang3.2svn emit due to the "-Wall" flag. There is one case of an uninitialised value in the ARM neon ISA description, and then a whole range of unused private fields that are pruned.
190 lines
6 KiB
C++
190 lines
6 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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* Copyright (c) 2011 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
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#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
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#include <cassert>
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#include <string>
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#include "mem/protocol/RequestStatus.hh"
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#include "mem/ruby/buffers/MessageBuffer.hh"
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#include "mem/ruby/system/System.hh"
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#include "mem/mem_object.hh"
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#include "mem/physical.hh"
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#include "mem/tport.hh"
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#include "params/RubyPort.hh"
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class AbstractController;
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class RubyPort : public MemObject
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{
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public:
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class M5Port : public QueuedSlavePort
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{
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private:
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SlavePacketQueue queue;
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RubyPort *ruby_port;
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RubySystem* ruby_system;
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bool _onRetryList;
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bool access_phys_mem;
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public:
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M5Port(const std::string &_name, RubyPort *_port,
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RubySystem*_system, bool _access_phys_mem);
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void hitCallback(PacketPtr pkt);
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void evictionCallback(const Address& address);
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unsigned deviceBlockSize() const;
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bool onRetryList()
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{ return _onRetryList; }
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void onRetryList(bool newVal)
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{ _onRetryList = newVal; }
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protected:
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virtual bool recvTimingReq(PacketPtr pkt);
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virtual Tick recvAtomic(PacketPtr pkt);
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virtual void recvFunctional(PacketPtr pkt);
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virtual AddrRangeList getAddrRanges() const;
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private:
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bool isPhysMemAddress(Addr addr);
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};
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friend class M5Port;
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class PioPort : public QueuedMasterPort
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{
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private:
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MasterPacketQueue queue;
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public:
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PioPort(const std::string &_name, RubyPort *_port);
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protected:
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virtual bool recvTimingResp(PacketPtr pkt);
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};
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friend class PioPort;
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struct SenderState : public Packet::SenderState
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{
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M5Port* port;
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SenderState(M5Port* _port) : port(_port)
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{}
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};
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typedef RubyPortParams Params;
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RubyPort(const Params *p);
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virtual ~RubyPort() {}
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void init();
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BaseMasterPort &getMasterPort(const std::string &if_name,
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PortID idx = InvalidPortID);
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BaseSlavePort &getSlavePort(const std::string &if_name,
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PortID idx = InvalidPortID);
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virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
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virtual int outstandingCount() const = 0;
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virtual bool isDeadlockEventScheduled() const = 0;
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virtual void descheduleDeadlockEvent() = 0;
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//
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// Called by the controller to give the sequencer a pointer.
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// A pointer to the controller is needed for atomic support.
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//
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void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
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int getId() { return m_version; }
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unsigned int drain(DrainManager *dm);
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protected:
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const std::string m_name;
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void ruby_hit_callback(PacketPtr pkt);
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void testDrainComplete();
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void ruby_eviction_callback(const Address& address);
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int m_version;
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AbstractController* m_controller;
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MessageBuffer* m_mandatory_q_ptr;
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PioPort pio_port;
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bool m_usingRubyTester;
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private:
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void addToRetryList(M5Port * port)
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{
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if (!port->onRetryList()) {
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port->onRetryList(true);
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retryList.push_back(port);
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waitingOnSequencer = true;
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}
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}
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unsigned int getChildDrainCount(DrainManager *dm);
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uint16_t m_port_id;
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uint64_t m_request_cnt;
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/** Vector of M5 Ports attached to this Ruby port. */
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typedef std::vector<M5Port*>::iterator CpuPortIter;
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std::vector<M5Port*> slave_ports;
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std::vector<PioPort*> master_ports;
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DrainManager *drainManager;
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RubySystem* ruby_system;
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System* system;
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//
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// Based on similar code in the M5 bus. Stores pointers to those ports
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// that should be called when the Sequencer becomes available after a stall.
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//
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std::list<M5Port*> retryList;
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bool waitingOnSequencer;
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bool access_phys_mem;
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};
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#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
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