c7b0901b97
It seems unecessary that the BankedArray class needs to schedule an event to figure out when the access ends. Instead only the time for the end of access needs to be tracked.
72 lines
2.5 KiB
C++
72 lines
2.5 KiB
C++
/*
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* Copyright (c) 2012 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Author: Brad Beckmann
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*
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*/
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#ifndef __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__
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#define __MEM_RUBY_SYSTEM_BANKEDARRAY_HH__
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#include <vector>
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#include "mem/ruby/common/TypeDefines.hh"
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#include "sim/core.hh"
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class BankedArray
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{
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private:
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unsigned int banks;
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Cycles accessLatency;
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unsigned int bankBits;
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unsigned int startIndexBit;
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class AccessRecord
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{
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public:
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AccessRecord() : idx(0), startAccess(0), endAccess(0) {}
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Index idx;
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Tick startAccess;
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Tick endAccess;
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};
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// If the tick event is scheduled then the bank is busy
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// otherwise, schedule the event and wait for it to complete
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std::vector<AccessRecord> busyBanks;
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unsigned int mapIndexToBank(Index idx);
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public:
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BankedArray(unsigned int banks, Cycles accessLatency, unsigned int startIndexBit);
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// Note: We try the access based on the cache index, not the address
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// This is so we don't get aliasing on blocks being replaced
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bool tryAccess(Index idx);
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};
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#endif
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