gem5/tests/configs/o3-timing-mp.py
Ali Saidi 90bd20aae2 tests: Always specify memory mode in every test system.
Previous to this change we didn't always set the memory mode which worked as
long as we never attempted to switch CPUs or checked that a CPU was in a
memory system with the correct mode. Future changes will make CPUs verify
that they're operating in the correct mode and thus we need to always set it.
2013-01-07 13:05:33 -05:00

74 lines
2.8 KiB
Python

# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Authors: Ron Dreslinski
import m5
from m5.objects import *
m5.util.addToPath('../configs/common')
from Caches import *
nb_cores = 4
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus,
physmem = SimpleDRAM(),
membus = CoherentBus(),
mem_mode = "timing")
# l2cache & bus
system.toL2Bus = CoherentBus(clock = '2GHz')
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
system.l2c.mem_side = system.membus.slave
# add L1 caches
for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
L1Cache(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
# connect memory to membus
system.physmem.port = system.membus.master
# connect system port to membus
system.system_port = system.membus.slave
# -----------------------
# run simulation
# -----------------------
root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
#root.trace.flags="Bus Cache"
#root.trace.flags = "BusAddrRanges"