1655 lines
45 KiB
C++
1655 lines
45 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#include <algorithm>
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#include "arch/utility.hh"
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#include "base/bigint.hh"
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#include "config/full_system.hh"
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#include "config/the_isa.hh"
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#include "cpu/inorder/resources/resource_list.hh"
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/first_stage.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource_pool.hh"
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#include "cpu/inorder/thread_context.hh"
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#include "cpu/inorder/thread_state.hh"
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#include "cpu/activity.hh"
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/simple_thread.hh"
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#include "cpu/thread_context.hh"
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#include "debug/Activity.hh"
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#include "debug/InOrderCPU.hh"
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#include "debug/RefCount.hh"
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#include "debug/SkedCache.hh"
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#include "mem/translating_port.hh"
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#include "params/InOrderCPU.hh"
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#include "sim/process.hh"
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#include "sim/stat_control.hh"
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#if FULL_SYSTEM
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#include "cpu/quiesce_event.hh"
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#include "sim/system.hh"
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#endif
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#if THE_ISA == ALPHA_ISA
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#include "arch/alpha/osfpal.hh"
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#endif
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using namespace std;
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using namespace TheISA;
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using namespace ThePipeline;
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InOrderCPU::TickEvent::TickEvent(InOrderCPU *c)
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: Event(CPU_Tick_Pri), cpu(c)
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{ }
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void
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InOrderCPU::TickEvent::process()
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{
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cpu->tick();
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}
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const char *
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InOrderCPU::TickEvent::description()
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{
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return "InOrderCPU tick event";
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}
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InOrderCPU::CPUEvent::CPUEvent(InOrderCPU *_cpu, CPUEventType e_type,
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Fault fault, ThreadID _tid, DynInstPtr inst,
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CPUEventPri event_pri)
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: Event(event_pri), cpu(_cpu)
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{
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setEvent(e_type, fault, _tid, inst);
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}
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std::string InOrderCPU::eventNames[NumCPUEvents] =
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{
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"ActivateThread",
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"ActivateNextReadyThread",
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"DeactivateThread",
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"HaltThread",
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"SuspendThread",
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"Trap",
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"InstGraduated",
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"SquashFromMemStall",
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"UpdatePCs"
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};
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void
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InOrderCPU::CPUEvent::process()
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{
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switch (cpuEventType)
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{
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case ActivateThread:
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cpu->activateThread(tid);
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break;
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case ActivateNextReadyThread:
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cpu->activateNextReadyThread();
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break;
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case DeactivateThread:
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cpu->deactivateThread(tid);
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break;
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case HaltThread:
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cpu->haltThread(tid);
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break;
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case SuspendThread:
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cpu->suspendThread(tid);
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break;
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case SquashFromMemStall:
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cpu->squashDueToMemStall(inst->squashingStage, inst->seqNum, tid);
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break;
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case Trap:
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DPRINTF(InOrderCPU, "Trapping CPU\n");
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cpu->trap(fault, tid, inst);
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cpu->resPool->trap(fault, tid, inst);
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break;
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default:
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fatal("Unrecognized Event Type %s", eventNames[cpuEventType]);
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}
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cpu->cpuEventRemoveList.push(this);
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}
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const char *
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InOrderCPU::CPUEvent::description()
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{
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return "InOrderCPU event";
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}
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void
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InOrderCPU::CPUEvent::scheduleEvent(int delay)
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{
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assert(!scheduled() || squashed());
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cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
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}
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void
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InOrderCPU::CPUEvent::unscheduleEvent()
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{
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if (scheduled())
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squash();
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}
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InOrderCPU::InOrderCPU(Params *params)
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: BaseCPU(params),
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cpu_id(params->cpu_id),
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coreType("default"),
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_status(Idle),
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tickEvent(this),
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stageWidth(params->stageWidth),
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timeBuffer(2 , 2),
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removeInstsThisCycle(false),
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activityRec(params->name, NumStages, 10, params->activity),
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#if FULL_SYSTEM
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system(params->system),
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physmem(system->physmem),
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#endif // FULL_SYSTEM
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#ifdef DEBUG
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cpuEventNum(0),
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resReqCount(0),
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#endif // DEBUG
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switchCount(0),
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deferRegistration(false/*params->deferRegistration*/),
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stageTracing(params->stageTracing),
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instsPerSwitch(0)
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{
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ThreadID active_threads;
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cpu_params = params;
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resPool = new ResourcePool(this, params);
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// Resize for Multithreading CPUs
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thread.resize(numThreads);
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#if FULL_SYSTEM
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active_threads = 1;
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#else
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active_threads = params->workload.size();
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if (active_threads > MaxThreads) {
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panic("Workload Size too large. Increase the 'MaxThreads'"
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"in your InOrder implementation or "
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"edit your workload size.");
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}
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if (active_threads > 1) {
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threadModel = (InOrderCPU::ThreadModel) params->threadModel;
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if (threadModel == SMT) {
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DPRINTF(InOrderCPU, "Setting Thread Model to SMT.\n");
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} else if (threadModel == SwitchOnCacheMiss) {
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DPRINTF(InOrderCPU, "Setting Thread Model to "
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"Switch On Cache Miss\n");
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}
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} else {
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threadModel = Single;
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}
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#endif
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// Bind the fetch & data ports from the resource pool.
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fetchPortIdx = resPool->getPortIdx(params->fetchMemPort);
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if (fetchPortIdx == 0) {
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fatal("Unable to find port to fetch instructions from.\n");
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}
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dataPortIdx = resPool->getPortIdx(params->dataMemPort);
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if (dataPortIdx == 0) {
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fatal("Unable to find port for data.\n");
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}
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for (ThreadID tid = 0; tid < numThreads; ++tid) {
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#if FULL_SYSTEM
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// SMT is not supported in FS mode yet.
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assert(numThreads == 1);
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thread[tid] = new Thread(this, 0);
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#else
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if (tid < (ThreadID)params->workload.size()) {
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DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n",
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tid, params->workload[tid]->prog_fname);
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thread[tid] =
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new Thread(this, tid, params->workload[tid]);
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} else {
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//Allocate Empty thread so M5 can use later
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//when scheduling threads to CPU
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Process* dummy_proc = params->workload[0];
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thread[tid] = new Thread(this, tid, dummy_proc);
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}
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// Eventually set this with parameters...
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asid[tid] = tid;
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#endif
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// Setup the TC that will serve as the interface to the threads/CPU.
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InOrderThreadContext *tc = new InOrderThreadContext;
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tc->cpu = this;
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tc->thread = thread[tid];
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// Give the thread the TC.
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thread[tid]->tc = tc;
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thread[tid]->setFuncExeInst(0);
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globalSeqNum[tid] = 1;
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// Add the TC to the CPU's list of TC's.
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this->threadContexts.push_back(tc);
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}
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// Initialize TimeBuffer Stage Queues
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for (int stNum=0; stNum < NumStages - 1; stNum++) {
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stageQueue[stNum] = new StageQueue(NumStages, NumStages);
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stageQueue[stNum]->id(stNum);
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}
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// Set Up Pipeline Stages
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for (int stNum=0; stNum < NumStages; stNum++) {
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if (stNum == 0)
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pipelineStage[stNum] = new FirstStage(params, stNum);
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else
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pipelineStage[stNum] = new PipelineStage(params, stNum);
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pipelineStage[stNum]->setCPU(this);
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pipelineStage[stNum]->setActiveThreads(&activeThreads);
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pipelineStage[stNum]->setTimeBuffer(&timeBuffer);
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// Take Care of 1st/Nth stages
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if (stNum > 0)
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pipelineStage[stNum]->setPrevStageQueue(stageQueue[stNum - 1]);
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if (stNum < NumStages - 1)
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pipelineStage[stNum]->setNextStageQueue(stageQueue[stNum]);
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}
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// Initialize thread specific variables
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for (ThreadID tid = 0; tid < numThreads; tid++) {
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archRegDepMap[tid].setCPU(this);
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nonSpecInstActive[tid] = false;
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nonSpecSeqNum[tid] = 0;
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squashSeqNum[tid] = MaxAddr;
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lastSquashCycle[tid] = 0;
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memset(intRegs[tid], 0, sizeof(intRegs[tid]));
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memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
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isa[tid].clear();
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// Define dummy instructions and resource requests to be used.
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dummyInst[tid] = new InOrderDynInst(this,
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thread[tid],
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0,
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tid,
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asid[tid]);
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dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
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}
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dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
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dummyReqInst->setSquashed();
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dummyReqInst->resetInstCount();
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dummyBufferInst = new InOrderDynInst(this, NULL, 0, 0, 0);
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dummyBufferInst->setSquashed();
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dummyBufferInst->resetInstCount();
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endOfSkedIt = skedCache.end();
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frontEndSked = createFrontEndSked();
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lastRunningCycle = curTick();
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// Reset CPU to reset state.
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#if FULL_SYSTEM
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Fault resetFault = new ResetFault();
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resetFault->invoke(tcBase());
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#endif
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// Schedule First Tick Event, CPU will reschedule itself from here on out.
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scheduleTickEvent(0);
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}
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InOrderCPU::~InOrderCPU()
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{
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delete resPool;
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SkedCacheIt sked_it = skedCache.begin();
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SkedCacheIt sked_end = skedCache.end();
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while (sked_it != sked_end) {
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delete (*sked_it).second;
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sked_it++;
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}
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skedCache.clear();
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}
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m5::hash_map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
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RSkedPtr
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InOrderCPU::createFrontEndSked()
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{
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RSkedPtr res_sked = new ResourceSked();
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int stage_num = 0;
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StageScheduler F(res_sked, stage_num++);
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StageScheduler D(res_sked, stage_num++);
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// FETCH
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F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
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F.needs(ICache, FetchUnit::InitiateFetch);
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// DECODE
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D.needs(ICache, FetchUnit::CompleteFetch);
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D.needs(Decode, DecodeUnit::DecodeInst);
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D.needs(BPred, BranchPredictor::PredictBranch);
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D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
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DPRINTF(SkedCache, "Resource Sked created for instruction \"front_end\"\n");
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return res_sked;
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}
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RSkedPtr
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InOrderCPU::createBackEndSked(DynInstPtr inst)
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{
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RSkedPtr res_sked = lookupSked(inst);
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if (res_sked != NULL) {
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DPRINTF(SkedCache, "Found %s in sked cache.\n",
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inst->instName());
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return res_sked;
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} else {
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res_sked = new ResourceSked();
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}
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int stage_num = ThePipeline::BackEndStartStage;
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StageScheduler X(res_sked, stage_num++);
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StageScheduler M(res_sked, stage_num++);
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StageScheduler W(res_sked, stage_num++);
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if (!inst->staticInst) {
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warn_once("Static Instruction Object Not Set. Can't Create"
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" Back End Schedule");
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return NULL;
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}
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// EXECUTE
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X.needs(RegManager, UseDefUnit::MarkDestRegs);
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for (int idx=0; idx < inst->numSrcRegs(); idx++) {
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if (!idx || !inst->isStore()) {
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X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
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}
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}
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//@todo: schedule non-spec insts to operate on this cycle
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// as long as all previous insts are done
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if ( inst->isNonSpeculative() ) {
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// skip execution of non speculative insts until later
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} else if ( inst->isMemRef() ) {
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if ( inst->isLoad() ) {
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X.needs(AGEN, AGENUnit::GenerateAddr);
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}
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} else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
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X.needs(MDU, MultDivUnit::StartMultDiv);
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} else {
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X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
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}
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// MEMORY
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if (!inst->isNonSpeculative()) {
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if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
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M.needs(MDU, MultDivUnit::EndMultDiv);
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}
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if ( inst->isLoad() ) {
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M.needs(DCache, CacheUnit::InitiateReadData);
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if (inst->splitInst)
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M.needs(DCache, CacheUnit::InitSecondSplitRead);
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} else if ( inst->isStore() ) {
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for (int i = 1; i < inst->numSrcRegs(); i++ ) {
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M.needs(RegManager, UseDefUnit::ReadSrcReg, i);
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}
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M.needs(AGEN, AGENUnit::GenerateAddr);
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M.needs(DCache, CacheUnit::InitiateWriteData);
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if (inst->splitInst)
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M.needs(DCache, CacheUnit::InitSecondSplitWrite);
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}
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}
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// WRITEBACK
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if (!inst->isNonSpeculative()) {
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if ( inst->isLoad() ) {
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W.needs(DCache, CacheUnit::CompleteReadData);
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if (inst->splitInst)
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W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
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} else if ( inst->isStore() ) {
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W.needs(DCache, CacheUnit::CompleteWriteData);
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if (inst->splitInst)
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W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
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}
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} else {
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// Finally, Execute Speculative Data
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if (inst->isMemRef()) {
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if (inst->isLoad()) {
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W.needs(AGEN, AGENUnit::GenerateAddr);
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W.needs(DCache, CacheUnit::InitiateReadData);
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if (inst->splitInst)
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W.needs(DCache, CacheUnit::InitSecondSplitRead);
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W.needs(DCache, CacheUnit::CompleteReadData);
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if (inst->splitInst)
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W.needs(DCache, CacheUnit::CompleteSecondSplitRead);
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} else if (inst->isStore()) {
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if ( inst->numSrcRegs() >= 2 ) {
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W.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
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}
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W.needs(AGEN, AGENUnit::GenerateAddr);
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W.needs(DCache, CacheUnit::InitiateWriteData);
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if (inst->splitInst)
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W.needs(DCache, CacheUnit::InitSecondSplitWrite);
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W.needs(DCache, CacheUnit::CompleteWriteData);
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if (inst->splitInst)
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W.needs(DCache, CacheUnit::CompleteSecondSplitWrite);
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}
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} else {
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W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
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}
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}
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W.needs(Grad, GraduationUnit::GraduateInst);
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for (int idx=0; idx < inst->numDestRegs(); idx++) {
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W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
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}
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// Insert Back Schedule into our cache of
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// resource schedules
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addToSkedCache(inst, res_sked);
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DPRINTF(SkedCache, "Back End Sked Created for instruction: %s (%08p)\n",
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inst->instName(), inst->getMachInst());
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res_sked->print();
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return res_sked;
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}
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|
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void
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InOrderCPU::regStats()
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{
|
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/* Register the Resource Pool's stats here.*/
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resPool->regStats();
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|
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/* Register for each Pipeline Stage */
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for (int stage_num=0; stage_num < ThePipeline::NumStages; stage_num++) {
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pipelineStage[stage_num]->regStats();
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}
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|
|
|
/* Register any of the InOrderCPU's stats here.*/
|
|
instsPerCtxtSwitch
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|
.name(name() + ".instsPerContextSwitch")
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|
.desc("Instructions Committed Per Context Switch")
|
|
.prereq(instsPerCtxtSwitch);
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|
|
numCtxtSwitches
|
|
.name(name() + ".contextSwitches")
|
|
.desc("Number of context switches");
|
|
|
|
comLoads
|
|
.name(name() + ".comLoads")
|
|
.desc("Number of Load instructions committed");
|
|
|
|
comStores
|
|
.name(name() + ".comStores")
|
|
.desc("Number of Store instructions committed");
|
|
|
|
comBranches
|
|
.name(name() + ".comBranches")
|
|
.desc("Number of Branches instructions committed");
|
|
|
|
comNops
|
|
.name(name() + ".comNops")
|
|
.desc("Number of Nop instructions committed");
|
|
|
|
comNonSpec
|
|
.name(name() + ".comNonSpec")
|
|
.desc("Number of Non-Speculative instructions committed");
|
|
|
|
comInts
|
|
.name(name() + ".comInts")
|
|
.desc("Number of Integer instructions committed");
|
|
|
|
comFloats
|
|
.name(name() + ".comFloats")
|
|
.desc("Number of Floating Point instructions committed");
|
|
|
|
timesIdled
|
|
.name(name() + ".timesIdled")
|
|
.desc("Number of times that the entire CPU went into an idle state and"
|
|
" unscheduled itself")
|
|
.prereq(timesIdled);
|
|
|
|
idleCycles
|
|
.name(name() + ".idleCycles")
|
|
.desc("Number of cycles cpu's stages were not processed");
|
|
|
|
runCycles
|
|
.name(name() + ".runCycles")
|
|
.desc("Number of cycles cpu stages are processed.");
|
|
|
|
activity
|
|
.name(name() + ".activity")
|
|
.desc("Percentage of cycles cpu is active")
|
|
.precision(6);
|
|
activity = (runCycles / numCycles) * 100;
|
|
|
|
threadCycles
|
|
.init(numThreads)
|
|
.name(name() + ".threadCycles")
|
|
.desc("Total Number of Cycles A Thread Was Active in CPU (Per-Thread)");
|
|
|
|
smtCycles
|
|
.name(name() + ".smtCycles")
|
|
.desc("Total number of cycles that the CPU was in SMT-mode");
|
|
|
|
committedInsts
|
|
.init(numThreads)
|
|
.name(name() + ".committedInsts")
|
|
.desc("Number of Instructions Simulated (Per-Thread)");
|
|
|
|
smtCommittedInsts
|
|
.init(numThreads)
|
|
.name(name() + ".smtCommittedInsts")
|
|
.desc("Number of SMT Instructions Simulated (Per-Thread)");
|
|
|
|
totalCommittedInsts
|
|
.name(name() + ".committedInsts_total")
|
|
.desc("Number of Instructions Simulated (Total)");
|
|
|
|
cpi
|
|
.name(name() + ".cpi")
|
|
.desc("CPI: Cycles Per Instruction (Per-Thread)")
|
|
.precision(6);
|
|
cpi = numCycles / committedInsts;
|
|
|
|
smtCpi
|
|
.name(name() + ".smt_cpi")
|
|
.desc("CPI: Total SMT-CPI")
|
|
.precision(6);
|
|
smtCpi = smtCycles / smtCommittedInsts;
|
|
|
|
totalCpi
|
|
.name(name() + ".cpi_total")
|
|
.desc("CPI: Total CPI of All Threads")
|
|
.precision(6);
|
|
totalCpi = numCycles / totalCommittedInsts;
|
|
|
|
ipc
|
|
.name(name() + ".ipc")
|
|
.desc("IPC: Instructions Per Cycle (Per-Thread)")
|
|
.precision(6);
|
|
ipc = committedInsts / numCycles;
|
|
|
|
smtIpc
|
|
.name(name() + ".smt_ipc")
|
|
.desc("IPC: Total SMT-IPC")
|
|
.precision(6);
|
|
smtIpc = smtCommittedInsts / smtCycles;
|
|
|
|
totalIpc
|
|
.name(name() + ".ipc_total")
|
|
.desc("IPC: Total IPC of All Threads")
|
|
.precision(6);
|
|
totalIpc = totalCommittedInsts / numCycles;
|
|
|
|
BaseCPU::regStats();
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::tick()
|
|
{
|
|
DPRINTF(InOrderCPU, "\n\nInOrderCPU: Ticking main, InOrderCPU.\n");
|
|
|
|
++numCycles;
|
|
|
|
bool pipes_idle = true;
|
|
|
|
//Tick each of the stages
|
|
for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
|
|
pipelineStage[stNum]->tick();
|
|
|
|
pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
|
|
}
|
|
|
|
if (pipes_idle)
|
|
idleCycles++;
|
|
else
|
|
runCycles++;
|
|
|
|
// Now advance the time buffers one tick
|
|
timeBuffer.advance();
|
|
for (int sqNum=0; sqNum < NumStages - 1; sqNum++) {
|
|
stageQueue[sqNum]->advance();
|
|
}
|
|
activityRec.advance();
|
|
|
|
// Any squashed events, or insts then remove them now
|
|
cleanUpRemovedEvents();
|
|
cleanUpRemovedInsts();
|
|
|
|
// Re-schedule CPU for this cycle
|
|
if (!tickEvent.scheduled()) {
|
|
if (_status == SwitchedOut) {
|
|
// increment stat
|
|
lastRunningCycle = curTick();
|
|
} else if (!activityRec.active()) {
|
|
DPRINTF(InOrderCPU, "sleeping CPU.\n");
|
|
lastRunningCycle = curTick();
|
|
timesIdled++;
|
|
} else {
|
|
//Tick next_tick = curTick() + cycles(1);
|
|
//tickEvent.schedule(next_tick);
|
|
schedule(&tickEvent, nextCycle(curTick() + 1));
|
|
DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n",
|
|
nextCycle(curTick() + 1));
|
|
}
|
|
}
|
|
|
|
tickThreadStats();
|
|
updateThreadPriority();
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::init()
|
|
{
|
|
if (!deferRegistration) {
|
|
registerThreadContexts();
|
|
}
|
|
|
|
// Set inSyscall so that the CPU doesn't squash when initially
|
|
// setting up registers.
|
|
for (ThreadID tid = 0; tid < numThreads; ++tid)
|
|
thread[tid]->inSyscall = true;
|
|
|
|
#if FULL_SYSTEM
|
|
for (ThreadID tid = 0; tid < numThreads; tid++) {
|
|
ThreadContext *src_tc = threadContexts[tid];
|
|
TheISA::initCPU(src_tc, src_tc->contextId());
|
|
}
|
|
#endif
|
|
|
|
// Clear inSyscall.
|
|
for (ThreadID tid = 0; tid < numThreads; ++tid)
|
|
thread[tid]->inSyscall = false;
|
|
|
|
// Call Initializiation Routine for Resource Pool
|
|
resPool->init();
|
|
}
|
|
|
|
Port*
|
|
InOrderCPU::getPort(const std::string &if_name, int idx)
|
|
{
|
|
return resPool->getPort(if_name, idx);
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
Fault
|
|
InOrderCPU::hwrei(ThreadID tid)
|
|
{
|
|
panic("hwrei: Unimplemented");
|
|
|
|
return NoFault;
|
|
}
|
|
|
|
|
|
bool
|
|
InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
|
|
{
|
|
panic("simPalCheck: Unimplemented");
|
|
|
|
return true;
|
|
}
|
|
|
|
|
|
Fault
|
|
InOrderCPU::getInterrupts()
|
|
{
|
|
// Check if there are any outstanding interrupts
|
|
return interrupts->getInterrupt(threadContexts[0]);
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::processInterrupts(Fault interrupt)
|
|
{
|
|
// Check for interrupts here. For now can copy the code that
|
|
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
|
// is the one that handles the interrupts.
|
|
// @todo: Possibly consolidate the interrupt checking code.
|
|
// @todo: Allow other threads to handle interrupts.
|
|
|
|
assert(interrupt != NoFault);
|
|
interrupts->updateIntrInfo(threadContexts[0]);
|
|
|
|
DPRINTF(InOrderCPU, "Interrupt %s being handled\n", interrupt->name());
|
|
|
|
// Note: Context ID ok here? Impl. of FS mode needs to revisit this
|
|
trap(interrupt, threadContexts[0]->contextId(), dummyBufferInst);
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::updateMemPorts()
|
|
{
|
|
// Update all ThreadContext's memory ports (Functional/Virtual
|
|
// Ports)
|
|
ThreadID size = thread.size();
|
|
for (ThreadID i = 0; i < size; ++i)
|
|
thread[i]->connectMemPorts(thread[i]->getTC());
|
|
}
|
|
#endif
|
|
|
|
void
|
|
InOrderCPU::trapContext(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
|
|
{
|
|
scheduleCpuEvent(Trap, fault, tid, inst, delay);
|
|
}
|
|
|
|
void
|
|
InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst)
|
|
{
|
|
fault->invoke(tcBase(tid), inst->staticInst);
|
|
}
|
|
|
|
void
|
|
InOrderCPU::squashFromMemStall(DynInstPtr inst, ThreadID tid, int delay)
|
|
{
|
|
scheduleCpuEvent(SquashFromMemStall, NoFault, tid, inst, delay);
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::squashDueToMemStall(int stage_num, InstSeqNum seq_num,
|
|
ThreadID tid)
|
|
{
|
|
DPRINTF(InOrderCPU, "Squashing Pipeline Stages Due to Memory Stall...\n");
|
|
|
|
// Squash all instructions in each stage including
|
|
// instruction that caused the squash (seq_num - 1)
|
|
// NOTE: The stage bandwidth needs to be cleared so thats why
|
|
// the stalling instruction is squashed as well. The stalled
|
|
// instruction is previously placed in another intermediate buffer
|
|
// while it's stall is being handled.
|
|
InstSeqNum squash_seq_num = seq_num - 1;
|
|
|
|
for (int stNum=stage_num; stNum >= 0 ; stNum--) {
|
|
pipelineStage[stNum]->squashDueToMemStall(squash_seq_num, tid);
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::scheduleCpuEvent(CPUEventType c_event, Fault fault,
|
|
ThreadID tid, DynInstPtr inst,
|
|
unsigned delay, CPUEventPri event_pri)
|
|
{
|
|
CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
|
|
event_pri);
|
|
|
|
Tick sked_tick = nextCycle(curTick() + ticks(delay));
|
|
if (delay >= 0) {
|
|
DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
|
|
eventNames[c_event], curTick() + delay, tid);
|
|
schedule(cpu_event, sked_tick);
|
|
} else {
|
|
cpu_event->process();
|
|
cpuEventRemoveList.push(cpu_event);
|
|
}
|
|
|
|
// Broadcast event to the Resource Pool
|
|
// Need to reset tid just in case this is a dummy instruction
|
|
inst->setTid(tid);
|
|
resPool->scheduleEvent(c_event, inst, 0, 0, tid);
|
|
}
|
|
|
|
bool
|
|
InOrderCPU::isThreadActive(ThreadID tid)
|
|
{
|
|
list<ThreadID>::iterator isActive =
|
|
std::find(activeThreads.begin(), activeThreads.end(), tid);
|
|
|
|
return (isActive != activeThreads.end());
|
|
}
|
|
|
|
bool
|
|
InOrderCPU::isThreadReady(ThreadID tid)
|
|
{
|
|
list<ThreadID>::iterator isReady =
|
|
std::find(readyThreads.begin(), readyThreads.end(), tid);
|
|
|
|
return (isReady != readyThreads.end());
|
|
}
|
|
|
|
bool
|
|
InOrderCPU::isThreadSuspended(ThreadID tid)
|
|
{
|
|
list<ThreadID>::iterator isSuspended =
|
|
std::find(suspendedThreads.begin(), suspendedThreads.end(), tid);
|
|
|
|
return (isSuspended != suspendedThreads.end());
|
|
}
|
|
|
|
void
|
|
InOrderCPU::activateNextReadyThread()
|
|
{
|
|
if (readyThreads.size() >= 1) {
|
|
ThreadID ready_tid = readyThreads.front();
|
|
|
|
// Activate in Pipeline
|
|
activateThread(ready_tid);
|
|
|
|
// Activate in Resource Pool
|
|
resPool->activateAll(ready_tid);
|
|
|
|
list<ThreadID>::iterator ready_it =
|
|
std::find(readyThreads.begin(), readyThreads.end(), ready_tid);
|
|
readyThreads.erase(ready_it);
|
|
} else {
|
|
DPRINTF(InOrderCPU,
|
|
"Attempting to activate new thread, but No Ready Threads to"
|
|
"activate.\n");
|
|
DPRINTF(InOrderCPU,
|
|
"Unable to switch to next active thread.\n");
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::activateThread(ThreadID tid)
|
|
{
|
|
if (isThreadSuspended(tid)) {
|
|
DPRINTF(InOrderCPU,
|
|
"Removing [tid:%i] from suspended threads list.\n", tid);
|
|
|
|
list<ThreadID>::iterator susp_it =
|
|
std::find(suspendedThreads.begin(), suspendedThreads.end(),
|
|
tid);
|
|
suspendedThreads.erase(susp_it);
|
|
}
|
|
|
|
if (threadModel == SwitchOnCacheMiss &&
|
|
numActiveThreads() == 1) {
|
|
DPRINTF(InOrderCPU,
|
|
"Ignoring activation of [tid:%i], since [tid:%i] is "
|
|
"already running.\n", tid, activeThreadId());
|
|
|
|
DPRINTF(InOrderCPU,"Placing [tid:%i] on ready threads list\n",
|
|
tid);
|
|
|
|
readyThreads.push_back(tid);
|
|
|
|
} else if (!isThreadActive(tid)) {
|
|
DPRINTF(InOrderCPU,
|
|
"Adding [tid:%i] to active threads list.\n", tid);
|
|
activeThreads.push_back(tid);
|
|
|
|
activateThreadInPipeline(tid);
|
|
|
|
thread[tid]->lastActivate = curTick();
|
|
|
|
tcBase(tid)->setStatus(ThreadContext::Active);
|
|
|
|
wakeCPU();
|
|
|
|
numCtxtSwitches++;
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::activateThreadInPipeline(ThreadID tid)
|
|
{
|
|
for (int stNum=0; stNum < NumStages; stNum++) {
|
|
pipelineStage[stNum]->activateThread(tid);
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::deactivateContext(ThreadID tid, int delay)
|
|
{
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Deactivating ...\n", tid);
|
|
|
|
scheduleCpuEvent(DeactivateThread, NoFault, tid, dummyInst[tid], delay);
|
|
|
|
// Be sure to signal that there's some activity so the CPU doesn't
|
|
// deschedule itself.
|
|
activityRec.activity();
|
|
|
|
_status = Running;
|
|
}
|
|
|
|
void
|
|
InOrderCPU::deactivateThread(ThreadID tid)
|
|
{
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Calling deactivate thread.\n", tid);
|
|
|
|
if (isThreadActive(tid)) {
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Removing from active threads list\n",
|
|
tid);
|
|
list<ThreadID>::iterator thread_it =
|
|
std::find(activeThreads.begin(), activeThreads.end(), tid);
|
|
|
|
removePipelineStalls(*thread_it);
|
|
|
|
activeThreads.erase(thread_it);
|
|
|
|
// Ideally, this should be triggered from the
|
|
// suspendContext/Thread functions
|
|
tcBase(tid)->setStatus(ThreadContext::Suspended);
|
|
}
|
|
|
|
assert(!isThreadActive(tid));
|
|
}
|
|
|
|
void
|
|
InOrderCPU::removePipelineStalls(ThreadID tid)
|
|
{
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Removing all pipeline stalls\n",
|
|
tid);
|
|
|
|
for (int stNum = 0; stNum < NumStages ; stNum++) {
|
|
pipelineStage[stNum]->removeStalls(tid);
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
InOrderCPU::updateThreadPriority()
|
|
{
|
|
if (activeThreads.size() > 1)
|
|
{
|
|
//DEFAULT TO ROUND ROBIN SCHEME
|
|
//e.g. Move highest priority to end of thread list
|
|
list<ThreadID>::iterator list_begin = activeThreads.begin();
|
|
list<ThreadID>::iterator list_end = activeThreads.end();
|
|
|
|
unsigned high_thread = *list_begin;
|
|
|
|
activeThreads.erase(list_begin);
|
|
|
|
activeThreads.push_back(high_thread);
|
|
}
|
|
}
|
|
|
|
inline void
|
|
InOrderCPU::tickThreadStats()
|
|
{
|
|
/** Keep track of cycles that each thread is active */
|
|
list<ThreadID>::iterator thread_it = activeThreads.begin();
|
|
while (thread_it != activeThreads.end()) {
|
|
threadCycles[*thread_it]++;
|
|
thread_it++;
|
|
}
|
|
|
|
// Keep track of cycles where SMT is active
|
|
if (activeThreads.size() > 1) {
|
|
smtCycles++;
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::activateContext(ThreadID tid, int delay)
|
|
{
|
|
DPRINTF(InOrderCPU,"[tid:%i]: Activating ...\n", tid);
|
|
|
|
|
|
scheduleCpuEvent(ActivateThread, NoFault, tid, dummyInst[tid], delay);
|
|
|
|
// Be sure to signal that there's some activity so the CPU doesn't
|
|
// deschedule itself.
|
|
activityRec.activity();
|
|
|
|
_status = Running;
|
|
}
|
|
|
|
void
|
|
InOrderCPU::activateNextReadyContext(int delay)
|
|
{
|
|
DPRINTF(InOrderCPU,"Activating next ready thread\n");
|
|
|
|
// NOTE: Add 5 to the event priority so that we always activate
|
|
// threads after we've finished deactivating, squashing,etc.
|
|
// other threads
|
|
scheduleCpuEvent(ActivateNextReadyThread, NoFault, 0/*tid*/, dummyInst[0],
|
|
delay, ActivateNextReadyThread_Pri);
|
|
|
|
// Be sure to signal that there's some activity so the CPU doesn't
|
|
// deschedule itself.
|
|
activityRec.activity();
|
|
|
|
_status = Running;
|
|
}
|
|
|
|
void
|
|
InOrderCPU::haltContext(ThreadID tid, int delay)
|
|
{
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
|
|
|
|
scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
|
|
|
|
activityRec.activity();
|
|
}
|
|
|
|
void
|
|
InOrderCPU::haltThread(ThreadID tid)
|
|
{
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Placing on Halted Threads List...\n", tid);
|
|
deactivateThread(tid);
|
|
squashThreadInPipeline(tid);
|
|
haltedThreads.push_back(tid);
|
|
|
|
tcBase(tid)->setStatus(ThreadContext::Halted);
|
|
|
|
if (threadModel == SwitchOnCacheMiss) {
|
|
activateNextReadyContext();
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::suspendContext(ThreadID tid, int delay)
|
|
{
|
|
scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
|
|
}
|
|
|
|
void
|
|
InOrderCPU::suspendThread(ThreadID tid)
|
|
{
|
|
DPRINTF(InOrderCPU, "[tid:%i]: Placing on Suspended Threads List...\n",
|
|
tid);
|
|
deactivateThread(tid);
|
|
suspendedThreads.push_back(tid);
|
|
thread[tid]->lastSuspend = curTick();
|
|
|
|
tcBase(tid)->setStatus(ThreadContext::Suspended);
|
|
}
|
|
|
|
void
|
|
InOrderCPU::squashThreadInPipeline(ThreadID tid)
|
|
{
|
|
//Squash all instructions in each stage
|
|
for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) {
|
|
pipelineStage[stNum]->squash(0 /*seq_num*/, tid);
|
|
}
|
|
}
|
|
|
|
PipelineStage*
|
|
InOrderCPU::getPipeStage(int stage_num)
|
|
{
|
|
return pipelineStage[stage_num];
|
|
}
|
|
|
|
|
|
RegIndex
|
|
InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType ®_type, ThreadID tid)
|
|
{
|
|
if (reg_idx < FP_Base_DepTag) {
|
|
reg_type = IntType;
|
|
return isa[tid].flattenIntIndex(reg_idx);
|
|
} else if (reg_idx < Ctrl_Base_DepTag) {
|
|
reg_type = FloatType;
|
|
reg_idx -= FP_Base_DepTag;
|
|
return isa[tid].flattenFloatIndex(reg_idx);
|
|
} else {
|
|
reg_type = MiscType;
|
|
return reg_idx - TheISA::Ctrl_Base_DepTag;
|
|
}
|
|
}
|
|
|
|
uint64_t
|
|
InOrderCPU::readIntReg(RegIndex reg_idx, ThreadID tid)
|
|
{
|
|
DPRINTF(IntRegs, "[tid:%i]: Reading Int. Reg %i as %x\n",
|
|
tid, reg_idx, intRegs[tid][reg_idx]);
|
|
|
|
return intRegs[tid][reg_idx];
|
|
}
|
|
|
|
FloatReg
|
|
InOrderCPU::readFloatReg(RegIndex reg_idx, ThreadID tid)
|
|
{
|
|
return floatRegs.f[tid][reg_idx];
|
|
}
|
|
|
|
FloatRegBits
|
|
InOrderCPU::readFloatRegBits(RegIndex reg_idx, ThreadID tid)
|
|
{;
|
|
return floatRegs.i[tid][reg_idx];
|
|
}
|
|
|
|
void
|
|
InOrderCPU::setIntReg(RegIndex reg_idx, uint64_t val, ThreadID tid)
|
|
{
|
|
if (reg_idx == TheISA::ZeroReg) {
|
|
DPRINTF(IntRegs, "[tid:%i]: Ignoring Setting of ISA-ZeroReg "
|
|
"(Int. Reg %i) to %x\n", tid, reg_idx, val);
|
|
return;
|
|
} else {
|
|
DPRINTF(IntRegs, "[tid:%i]: Setting Int. Reg %i to %x\n",
|
|
tid, reg_idx, val);
|
|
|
|
intRegs[tid][reg_idx] = val;
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::setFloatReg(RegIndex reg_idx, FloatReg val, ThreadID tid)
|
|
{
|
|
floatRegs.f[tid][reg_idx] = val;
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::setFloatRegBits(RegIndex reg_idx, FloatRegBits val, ThreadID tid)
|
|
{
|
|
floatRegs.i[tid][reg_idx] = val;
|
|
}
|
|
|
|
uint64_t
|
|
InOrderCPU::readRegOtherThread(unsigned reg_idx, ThreadID tid)
|
|
{
|
|
// If Default value is set, then retrieve target thread
|
|
if (tid == InvalidThreadID) {
|
|
tid = TheISA::getTargetThread(tcBase(tid));
|
|
}
|
|
|
|
if (reg_idx < FP_Base_DepTag) {
|
|
// Integer Register File
|
|
return readIntReg(reg_idx, tid);
|
|
} else if (reg_idx < Ctrl_Base_DepTag) {
|
|
// Float Register File
|
|
reg_idx -= FP_Base_DepTag;
|
|
return readFloatRegBits(reg_idx, tid);
|
|
} else {
|
|
reg_idx -= Ctrl_Base_DepTag;
|
|
return readMiscReg(reg_idx, tid); // Misc. Register File
|
|
}
|
|
}
|
|
void
|
|
InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
|
ThreadID tid)
|
|
{
|
|
// If Default value is set, then retrieve target thread
|
|
if (tid == InvalidThreadID) {
|
|
tid = TheISA::getTargetThread(tcBase(tid));
|
|
}
|
|
|
|
if (reg_idx < FP_Base_DepTag) { // Integer Register File
|
|
setIntReg(reg_idx, val, tid);
|
|
} else if (reg_idx < Ctrl_Base_DepTag) { // Float Register File
|
|
reg_idx -= FP_Base_DepTag;
|
|
setFloatRegBits(reg_idx, val, tid);
|
|
} else {
|
|
reg_idx -= Ctrl_Base_DepTag;
|
|
setMiscReg(reg_idx, val, tid); // Misc. Register File
|
|
}
|
|
}
|
|
|
|
MiscReg
|
|
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
|
|
{
|
|
return isa[tid].readMiscRegNoEffect(misc_reg);
|
|
}
|
|
|
|
MiscReg
|
|
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
|
|
{
|
|
return isa[tid].readMiscReg(misc_reg, tcBase(tid));
|
|
}
|
|
|
|
void
|
|
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
|
|
{
|
|
isa[tid].setMiscRegNoEffect(misc_reg, val);
|
|
}
|
|
|
|
void
|
|
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
|
|
{
|
|
isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
|
|
}
|
|
|
|
|
|
InOrderCPU::ListIt
|
|
InOrderCPU::addInst(DynInstPtr inst)
|
|
{
|
|
ThreadID tid = inst->readTid();
|
|
|
|
instList[tid].push_back(inst);
|
|
|
|
return --(instList[tid].end());
|
|
}
|
|
|
|
InOrderCPU::ListIt
|
|
InOrderCPU::findInst(InstSeqNum seq_num, ThreadID tid)
|
|
{
|
|
ListIt it = instList[tid].begin();
|
|
ListIt end = instList[tid].end();
|
|
|
|
while (it != end) {
|
|
if ((*it)->seqNum == seq_num)
|
|
return it;
|
|
else if ((*it)->seqNum > seq_num)
|
|
break;
|
|
|
|
it++;
|
|
}
|
|
|
|
return instList[tid].end();
|
|
}
|
|
|
|
void
|
|
InOrderCPU::updateContextSwitchStats()
|
|
{
|
|
// Set Average Stat Here, then reset to 0
|
|
instsPerCtxtSwitch = instsPerSwitch;
|
|
instsPerSwitch = 0;
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::instDone(DynInstPtr inst, ThreadID tid)
|
|
{
|
|
// Set the nextPC to be fetched if this is the last instruction
|
|
// committed
|
|
// ========
|
|
// This contributes to the precise state of the CPU
|
|
// which can be used when restoring a thread to the CPU after after any
|
|
// type of context switching activity (fork, exception, etc.)
|
|
TheISA::PCState comm_pc = inst->pcState();
|
|
lastCommittedPC[tid] = comm_pc;
|
|
TheISA::advancePC(comm_pc, inst->staticInst);
|
|
pcState(comm_pc, tid);
|
|
|
|
//@todo: may be unnecessary with new-ISA-specific branch handling code
|
|
if (inst->isControl()) {
|
|
thread[tid]->lastGradIsBranch = true;
|
|
thread[tid]->lastBranchPC = inst->pcState();
|
|
TheISA::advancePC(thread[tid]->lastBranchPC, inst->staticInst);
|
|
} else {
|
|
thread[tid]->lastGradIsBranch = false;
|
|
}
|
|
|
|
|
|
// Finalize Trace Data For Instruction
|
|
if (inst->traceData) {
|
|
//inst->traceData->setCycle(curTick());
|
|
inst->traceData->setFetchSeq(inst->seqNum);
|
|
//inst->traceData->setCPSeq(cpu->tcBase(tid)->numInst);
|
|
inst->traceData->dump();
|
|
delete inst->traceData;
|
|
inst->traceData = NULL;
|
|
}
|
|
|
|
// Increment active thread's instruction count
|
|
instsPerSwitch++;
|
|
|
|
// Increment thread-state's instruction count
|
|
thread[tid]->numInst++;
|
|
|
|
// Increment thread-state's instruction stats
|
|
thread[tid]->numInsts++;
|
|
|
|
// Count committed insts per thread stats
|
|
committedInsts[tid]++;
|
|
|
|
// Count total insts committed stat
|
|
totalCommittedInsts++;
|
|
|
|
// Count SMT-committed insts per thread stat
|
|
if (numActiveThreads() > 1) {
|
|
smtCommittedInsts[tid]++;
|
|
}
|
|
|
|
// Instruction-Mix Stats
|
|
if (inst->isLoad()) {
|
|
comLoads++;
|
|
} else if (inst->isStore()) {
|
|
comStores++;
|
|
} else if (inst->isControl()) {
|
|
comBranches++;
|
|
} else if (inst->isNop()) {
|
|
comNops++;
|
|
} else if (inst->isNonSpeculative()) {
|
|
comNonSpec++;
|
|
} else if (inst->isInteger()) {
|
|
comInts++;
|
|
} else if (inst->isFloating()) {
|
|
comFloats++;
|
|
}
|
|
|
|
// Check for instruction-count-based events.
|
|
comInstEventQueue[tid]->serviceEvents(thread[tid]->numInst);
|
|
|
|
// Broadcast to other resources an instruction
|
|
// has been completed
|
|
resPool->scheduleEvent((CPUEventType)ResourcePool::InstGraduated, inst,
|
|
0, 0, tid);
|
|
|
|
// Finally, remove instruction from CPU
|
|
removeInst(inst);
|
|
}
|
|
|
|
// currently unused function, but substitute repetitive code w/this function
|
|
// call
|
|
void
|
|
InOrderCPU::addToRemoveList(DynInstPtr inst)
|
|
{
|
|
removeInstsThisCycle = true;
|
|
if (!inst->isRemoveList()) {
|
|
DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
|
|
"[sn:%lli] to remove list\n",
|
|
inst->threadNumber, inst->pcState(), inst->seqNum);
|
|
inst->setRemoveList();
|
|
removeList.push(inst->getInstListIt());
|
|
} else {
|
|
DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
|
|
"[sn:%lli], already remove list\n",
|
|
inst->threadNumber, inst->pcState(), inst->seqNum);
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
InOrderCPU::removeInst(DynInstPtr inst)
|
|
{
|
|
DPRINTF(InOrderCPU, "Removing graduated instruction [tid:%i] PC %s "
|
|
"[sn:%lli]\n",
|
|
inst->threadNumber, inst->pcState(), inst->seqNum);
|
|
|
|
removeInstsThisCycle = true;
|
|
|
|
// Remove the instruction.
|
|
if (!inst->isRemoveList()) {
|
|
DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
|
|
"[sn:%lli] to remove list\n",
|
|
inst->threadNumber, inst->pcState(), inst->seqNum);
|
|
inst->setRemoveList();
|
|
removeList.push(inst->getInstListIt());
|
|
} else {
|
|
DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i] PC %s "
|
|
"[sn:%lli], already on remove list\n",
|
|
inst->threadNumber, inst->pcState(), inst->seqNum);
|
|
}
|
|
|
|
}
|
|
|
|
void
|
|
InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
|
|
{
|
|
//assert(!instList[tid].empty());
|
|
|
|
removeInstsThisCycle = true;
|
|
|
|
ListIt inst_iter = instList[tid].end();
|
|
|
|
inst_iter--;
|
|
|
|
DPRINTF(InOrderCPU, "Squashing instructions from CPU instruction "
|
|
"list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n",
|
|
tid, seq_num, (*inst_iter)->seqNum);
|
|
|
|
while ((*inst_iter)->seqNum > seq_num) {
|
|
|
|
bool break_loop = (inst_iter == instList[tid].begin());
|
|
|
|
squashInstIt(inst_iter, tid);
|
|
|
|
inst_iter--;
|
|
|
|
if (break_loop)
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
inline void
|
|
InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
|
|
{
|
|
DynInstPtr inst = (*inst_it);
|
|
if (inst->threadNumber == tid) {
|
|
DPRINTF(InOrderCPU, "Squashing instruction, "
|
|
"[tid:%i] [sn:%lli] PC %s\n",
|
|
inst->threadNumber,
|
|
inst->seqNum,
|
|
inst->pcState());
|
|
|
|
inst->setSquashed();
|
|
archRegDepMap[tid].remove(inst);
|
|
|
|
if (!inst->isRemoveList()) {
|
|
DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
|
|
"[sn:%lli] to remove list\n",
|
|
inst->threadNumber, inst->pcState(),
|
|
inst->seqNum);
|
|
inst->setRemoveList();
|
|
removeList.push(inst_it);
|
|
} else {
|
|
DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
|
|
" PC %s [sn:%lli], already on remove list\n",
|
|
inst->threadNumber, inst->pcState(),
|
|
inst->seqNum);
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::cleanUpRemovedInsts()
|
|
{
|
|
while (!removeList.empty()) {
|
|
DPRINTF(InOrderCPU, "Removing instruction, "
|
|
"[tid:%i] [sn:%lli] PC %s\n",
|
|
(*removeList.front())->threadNumber,
|
|
(*removeList.front())->seqNum,
|
|
(*removeList.front())->pcState());
|
|
|
|
DynInstPtr inst = *removeList.front();
|
|
ThreadID tid = inst->threadNumber;
|
|
|
|
// Remove From Register Dependency Map, If Necessary
|
|
// archRegDepMap[tid].remove(inst);
|
|
|
|
// Clear if Non-Speculative
|
|
if (inst->staticInst &&
|
|
inst->seqNum == nonSpecSeqNum[tid] &&
|
|
nonSpecInstActive[tid] == true) {
|
|
nonSpecInstActive[tid] = false;
|
|
}
|
|
|
|
inst->onInstList = false;
|
|
|
|
instList[tid].erase(removeList.front());
|
|
|
|
removeList.pop();
|
|
}
|
|
|
|
removeInstsThisCycle = false;
|
|
}
|
|
|
|
void
|
|
InOrderCPU::cleanUpRemovedEvents()
|
|
{
|
|
while (!cpuEventRemoveList.empty()) {
|
|
Event *cpu_event = cpuEventRemoveList.front();
|
|
cpuEventRemoveList.pop();
|
|
delete cpu_event;
|
|
}
|
|
}
|
|
|
|
|
|
void
|
|
InOrderCPU::dumpInsts()
|
|
{
|
|
int num = 0;
|
|
|
|
ListIt inst_list_it = instList[0].begin();
|
|
|
|
cprintf("Dumping Instruction List\n");
|
|
|
|
while (inst_list_it != instList[0].end()) {
|
|
cprintf("Instruction:%i\nPC:%s\n[tid:%i]\n[sn:%lli]\nIssued:%i\n"
|
|
"Squashed:%i\n\n",
|
|
num, (*inst_list_it)->pcState(),
|
|
(*inst_list_it)->threadNumber,
|
|
(*inst_list_it)->seqNum, (*inst_list_it)->isIssued(),
|
|
(*inst_list_it)->isSquashed());
|
|
inst_list_it++;
|
|
++num;
|
|
}
|
|
}
|
|
|
|
void
|
|
InOrderCPU::wakeCPU()
|
|
{
|
|
if (/*activityRec.active() || */tickEvent.scheduled()) {
|
|
DPRINTF(Activity, "CPU already running.\n");
|
|
return;
|
|
}
|
|
|
|
DPRINTF(Activity, "Waking up CPU\n");
|
|
|
|
Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
|
|
|
|
idleCycles += extra_cycles;
|
|
for (int stage_num = 0; stage_num < NumStages; stage_num++) {
|
|
pipelineStage[stage_num]->idleCycles += extra_cycles;
|
|
}
|
|
|
|
numCycles += extra_cycles;
|
|
|
|
schedule(&tickEvent, nextCycle(curTick()));
|
|
}
|
|
|
|
#if FULL_SYSTEM
|
|
|
|
void
|
|
InOrderCPU::wakeup()
|
|
{
|
|
if (thread[0]->status() != ThreadContext::Suspended)
|
|
return;
|
|
|
|
wakeCPU();
|
|
|
|
DPRINTF(Quiesce, "Suspended Processor woken\n");
|
|
threadContexts[0]->activate();
|
|
}
|
|
#endif
|
|
|
|
#if !FULL_SYSTEM
|
|
void
|
|
InOrderCPU::syscall(int64_t callnum, ThreadID tid)
|
|
{
|
|
DPRINTF(InOrderCPU, "[tid:%i] Executing syscall().\n\n", tid);
|
|
|
|
DPRINTF(Activity,"Activity: syscall() called.\n");
|
|
|
|
// Temporarily increase this by one to account for the syscall
|
|
// instruction.
|
|
++(this->thread[tid]->funcExeInst);
|
|
|
|
// Execute the actual syscall.
|
|
this->thread[tid]->syscall(callnum);
|
|
|
|
// Decrease funcExeInst by one as the normal commit will handle
|
|
// incrementing it.
|
|
--(this->thread[tid]->funcExeInst);
|
|
|
|
// Clear Non-Speculative Block Variable
|
|
nonSpecInstActive[tid] = false;
|
|
}
|
|
#endif
|
|
|
|
TheISA::TLB*
|
|
InOrderCPU::getITBPtr()
|
|
{
|
|
CacheUnit *itb_res =
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(fetchPortIdx));
|
|
return itb_res->tlb();
|
|
}
|
|
|
|
|
|
TheISA::TLB*
|
|
InOrderCPU::getDTBPtr()
|
|
{
|
|
CacheUnit *dtb_res =
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
|
|
return dtb_res->tlb();
|
|
}
|
|
|
|
Fault
|
|
InOrderCPU::read(DynInstPtr inst, Addr addr,
|
|
uint8_t *data, unsigned size, unsigned flags)
|
|
{
|
|
//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
|
|
// you want to run w/out caches?
|
|
CacheUnit *cache_res =
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
|
|
|
|
return cache_res->read(inst, addr, data, size, flags);
|
|
}
|
|
|
|
Fault
|
|
InOrderCPU::write(DynInstPtr inst, uint8_t *data, unsigned size,
|
|
Addr addr, unsigned flags, uint64_t *write_res)
|
|
{
|
|
//@TODO: Generalize name "CacheUnit" to "MemUnit" just in case
|
|
// you want to run w/out caches?
|
|
CacheUnit *cache_res =
|
|
dynamic_cast<CacheUnit*>(resPool->getResource(dataPortIdx));
|
|
return cache_res->write(inst, data, size, addr, flags, write_res);
|
|
}
|