gem5/src/mem/protocol/MOESI_AMD_Base.slicc
2016-01-19 14:28:22 -05:00

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protocol "MOESI_AMD_Base";
include "RubySlicc_interfaces.slicc";
include "MOESI_AMD_Base-msg.sm";
include "MOESI_AMD_Base-CorePair.sm";
include "MOESI_AMD_Base-L3cache.sm";
include "MOESI_AMD_Base-dir.sm";