6df196b71e
DynInst is extremely large the hope is that this re-organization will put the most used members close to each other.
1058 lines
36 KiB
C++
1058 lines
36 KiB
C++
/*
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* Copyright (c) 2011 ARM Limited
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* Copyright (c) 2009 The University of Edinburgh
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Timothy M. Jones
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*/
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#ifndef __CPU_BASE_DYN_INST_HH__
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#define __CPU_BASE_DYN_INST_HH__
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#include <bitset>
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#include <list>
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#include <string>
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#include <queue>
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#include "arch/utility.hh"
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#include "base/trace.hh"
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#include "config/the_isa.hh"
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#include "cpu/checker/cpu.hh"
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#include "cpu/o3/comm.hh"
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#include "cpu/exetrace.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/op_class.hh"
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#include "cpu/static_inst.hh"
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#include "cpu/translation.hh"
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#include "mem/packet.hh"
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#include "sim/byteswap.hh"
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#include "sim/fault_fwd.hh"
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#include "sim/system.hh"
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#include "sim/tlb.hh"
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/**
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* @file
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* Defines a dynamic instruction context.
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*/
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template <class Impl>
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class BaseDynInst : public RefCounted
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{
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public:
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// Typedef for the CPU.
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typedef typename Impl::CPUType ImplCPU;
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typedef typename ImplCPU::ImplState ImplState;
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// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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// Integer register type.
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typedef TheISA::IntReg IntReg;
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// Floating point register type.
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typedef TheISA::FloatReg FloatReg;
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// The DynInstPtr type.
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef RefCountingPtr<BaseDynInst<Impl> > BaseDynInstPtr;
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// The list of instructions iterator type.
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typedef typename std::list<DynInstPtr>::iterator ListIt;
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enum {
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MaxInstSrcRegs = TheISA::MaxInstSrcRegs, /// Max source regs
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MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
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};
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union Result {
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uint64_t integer;
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double dbl;
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void set(uint64_t i) { integer = i; }
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void set(double d) { dbl = d; }
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void get(uint64_t& i) { i = integer; }
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void get(double& d) { d = dbl; }
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};
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protected:
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enum Status {
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IqEntry, /// Instruction is in the IQ
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RobEntry, /// Instruction is in the ROB
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LsqEntry, /// Instruction is in the LSQ
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Completed, /// Instruction has completed
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ResultReady, /// Instruction has its result
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CanIssue, /// Instruction can issue and execute
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Issued, /// Instruction has issued
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Executed, /// Instruction has executed
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CanCommit, /// Instruction can commit
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AtCommit, /// Instruction has reached commit
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Committed, /// Instruction has committed
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Squashed, /// Instruction is squashed
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SquashedInIQ, /// Instruction is squashed in the IQ
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SquashedInLSQ, /// Instruction is squashed in the LSQ
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SquashedInROB, /// Instruction is squashed in the ROB
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RecoverInst, /// Is a recover instruction
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BlockingInst, /// Is a blocking instruction
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ThreadsyncWait, /// Is a thread synchronization instruction
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SerializeBefore, /// Needs to serialize on
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/// instructions ahead of it
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SerializeAfter, /// Needs to serialize instructions behind it
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SerializeHandled, /// Serialization has been handled
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NumStatus
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};
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enum Flags {
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TranslationStarted,
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TranslationCompleted,
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PossibleLoadViolation,
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HitExternalSnoop,
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EffAddrValid,
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RecordResult,
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Predicate,
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PredTaken,
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/** Whether or not the effective address calculation is completed.
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* @todo: Consider if this is necessary or not.
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*/
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EACalcDone,
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IsUncacheable,
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ReqMade,
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MemOpDone,
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MaxFlags
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};
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public:
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/** The sequence number of the instruction. */
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InstSeqNum seqNum;
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/** The StaticInst used by this BaseDynInst. */
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StaticInstPtr staticInst;
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/** Pointer to the Impl's CPU object. */
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ImplCPU *cpu;
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/** Pointer to the thread state. */
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ImplState *thread;
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/** The kind of fault this instruction has generated. */
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Fault fault;
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/** InstRecord that tracks this instructions. */
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Trace::InstRecord *traceData;
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protected:
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/** The result of the instruction; assumes an instruction can have many
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* destination registers.
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*/
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std::queue<Result> instResult;
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/** PC state for this instruction. */
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TheISA::PCState pc;
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/* An amalgamation of a lot of boolean values into one */
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std::bitset<MaxFlags> instFlags;
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/** The status of this BaseDynInst. Several bits can be set. */
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std::bitset<NumStatus> status;
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/** Whether or not the source register is ready.
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* @todo: Not sure this should be here vs the derived class.
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*/
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std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
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public:
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/** The thread this instruction is from. */
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ThreadID threadNumber;
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/** Iterator pointing to this BaseDynInst in the list of all insts. */
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ListIt instListIt;
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////////////////////// Branch Data ///////////////
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/** Predicted PC state after this instruction. */
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TheISA::PCState predPC;
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/** The Macroop if one exists */
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StaticInstPtr macroop;
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/** How many source registers are ready. */
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uint8_t readyRegs;
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public:
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/////////////////////// Load Store Data //////////////////////
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/** The effective virtual address (lds & stores only). */
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Addr effAddr;
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/** The effective physical address. */
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Addr physEffAddr;
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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/** data address space ID, for loads & stores. */
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short asid;
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/** The size of the request */
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uint8_t effSize;
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/** Pointer to the data for the memory access. */
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uint8_t *memData;
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/** Load queue index. */
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int16_t lqIdx;
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/** Store queue index. */
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int16_t sqIdx;
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/////////////////////// TLB Miss //////////////////////
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/**
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* Saved memory requests (needed when the DTB address translation is
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* delayed due to a hw page table walk).
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*/
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RequestPtr savedReq;
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RequestPtr savedSreqLow;
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RequestPtr savedSreqHigh;
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/////////////////////// Checker //////////////////////
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// Need a copy of main request pointer to verify on writes.
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RequestPtr reqToVerify;
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private:
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/** Instruction effective address.
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* @todo: Consider if this is necessary or not.
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*/
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Addr instEffAddr;
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protected:
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/** Flattened register index of the destination registers of this
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* instruction.
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*/
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TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
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/** Physical register index of the destination registers of this
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* instruction.
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*/
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PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
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/** Physical register index of the source registers of this
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* instruction.
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*/
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PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
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/** Physical register index of the previous producers of the
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* architected destinations.
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*/
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PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
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public:
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/** Records changes to result? */
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void recordResult(bool f) { instFlags[RecordResult] = f; }
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/** Is the effective virtual address valid. */
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bool effAddrValid() const { return instFlags[EffAddrValid]; }
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/** Whether or not the memory operation is done. */
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bool memOpDone() const { return instFlags[MemOpDone]; }
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void memOpDone(bool f) { instFlags[MemOpDone] = f; }
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////////////////////////////////////////////
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//
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// INSTRUCTION EXECUTION
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//
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////////////////////////////////////////////
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void demapPage(Addr vaddr, uint64_t asn)
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{
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cpu->demapPage(vaddr, asn);
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}
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void demapInstPage(Addr vaddr, uint64_t asn)
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{
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cpu->demapPage(vaddr, asn);
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}
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void demapDataPage(Addr vaddr, uint64_t asn)
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{
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cpu->demapPage(vaddr, asn);
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}
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Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
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Fault writeMem(uint8_t *data, unsigned size,
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Addr addr, unsigned flags, uint64_t *res);
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/** Splits a request in two if it crosses a dcache block. */
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void splitRequest(RequestPtr req, RequestPtr &sreqLow,
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RequestPtr &sreqHigh);
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/** Initiate a DTB address translation. */
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void initiateTranslation(RequestPtr req, RequestPtr sreqLow,
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RequestPtr sreqHigh, uint64_t *res,
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BaseTLB::Mode mode);
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/** Finish a DTB address translation. */
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void finishTranslation(WholeTranslationState *state);
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/** True if the DTB address translation has started. */
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bool translationStarted() const { return instFlags[TranslationStarted]; }
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void translationStarted(bool f) { instFlags[TranslationStarted] = f; }
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/** True if the DTB address translation has completed. */
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bool translationCompleted() const { return instFlags[TranslationCompleted]; }
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void translationCompleted(bool f) { instFlags[TranslationCompleted] = f; }
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/** True if this address was found to match a previous load and they issued
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* out of order. If that happend, then it's only a problem if an incoming
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* snoop invalidate modifies the line, in which case we need to squash.
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* If nothing modified the line the order doesn't matter.
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*/
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bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
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void possibleLoadViolation(bool f) { instFlags[PossibleLoadViolation] = f; }
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/** True if the address hit a external snoop while sitting in the LSQ.
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* If this is true and a older instruction sees it, this instruction must
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* reexecute
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*/
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bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
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void hitExternalSnoop(bool f) { instFlags[HitExternalSnoop] = f; }
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/**
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* Returns true if the DTB address translation is being delayed due to a hw
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* page table walk.
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*/
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bool isTranslationDelayed() const
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{
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return (translationStarted() && !translationCompleted());
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}
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public:
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#ifdef DEBUG
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void dumpSNList();
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#endif
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/** Returns the physical register index of the i'th destination
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* register.
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*/
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PhysRegIndex renamedDestRegIdx(int idx) const
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{
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return _destRegIdx[idx];
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}
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/** Returns the physical register index of the i'th source register. */
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PhysRegIndex renamedSrcRegIdx(int idx) const
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{
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assert(TheISA::MaxInstSrcRegs > idx);
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return _srcRegIdx[idx];
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}
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/** Returns the flattened register index of the i'th destination
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* register.
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*/
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TheISA::RegIndex flattenedDestRegIdx(int idx) const
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{
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return _flatDestRegIdx[idx];
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}
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/** Returns the physical register index of the previous physical register
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* that remapped to the same logical register index.
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*/
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PhysRegIndex prevDestRegIdx(int idx) const
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{
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return _prevDestRegIdx[idx];
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}
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/** Renames a destination register to a physical register. Also records
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* the previous physical register that the logical register mapped to.
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*/
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void renameDestReg(int idx,
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PhysRegIndex renamed_dest,
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PhysRegIndex previous_rename)
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{
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_destRegIdx[idx] = renamed_dest;
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_prevDestRegIdx[idx] = previous_rename;
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}
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/** Renames a source logical register to the physical register which
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* has/will produce that logical register's result.
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* @todo: add in whether or not the source register is ready.
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*/
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void renameSrcReg(int idx, PhysRegIndex renamed_src)
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{
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_srcRegIdx[idx] = renamed_src;
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}
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/** Flattens a destination architectural register index into a logical
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* index.
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*/
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void flattenDestReg(int idx, TheISA::RegIndex flattened_dest)
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{
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_flatDestRegIdx[idx] = flattened_dest;
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}
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/** BaseDynInst constructor given a binary instruction.
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* @param staticInst A StaticInstPtr to the underlying instruction.
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* @param pc The PC state for the instruction.
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* @param predPC The predicted next PC state for the instruction.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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*/
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BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop,
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TheISA::PCState pc, TheISA::PCState predPC,
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InstSeqNum seq_num, ImplCPU *cpu);
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/** BaseDynInst constructor given a StaticInst pointer.
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* @param _staticInst The StaticInst for this BaseDynInst.
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*/
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BaseDynInst(StaticInstPtr staticInst, StaticInstPtr macroop);
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/** BaseDynInst destructor. */
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~BaseDynInst();
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private:
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/** Function to initialize variables in the constructors. */
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void initVars();
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public:
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/** Dumps out contents of this BaseDynInst. */
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void dump();
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/** Dumps out contents of this BaseDynInst into given string. */
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void dump(std::string &outstring);
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/** Read this CPU's ID. */
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int cpuId() { return cpu->cpuId(); }
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/** Read this CPU's data requestor ID */
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MasterID masterId() { return cpu->dataMasterId(); }
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/** Read this context's system-wide ID **/
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int contextId() { return thread->contextId(); }
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/** Returns the fault type. */
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Fault getFault() { return fault; }
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/** Checks whether or not this instruction has had its branch target
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* calculated yet. For now it is not utilized and is hacked to be
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* always false.
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* @todo: Actually use this instruction.
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*/
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bool doneTargCalc() { return false; }
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/** Set the predicted target of this current instruction. */
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void setPredTarg(const TheISA::PCState &_predPC)
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{
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predPC = _predPC;
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}
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const TheISA::PCState &readPredTarg() { return predPC; }
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/** Returns the predicted PC immediately after the branch. */
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Addr predInstAddr() { return predPC.instAddr(); }
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/** Returns the predicted PC two instructions after the branch */
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Addr predNextInstAddr() { return predPC.nextInstAddr(); }
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/** Returns the predicted micro PC after the branch */
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Addr predMicroPC() { return predPC.microPC(); }
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/** Returns whether the instruction was predicted taken or not. */
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bool readPredTaken()
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{
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return instFlags[PredTaken];
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}
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void setPredTaken(bool predicted_taken)
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{
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instFlags[PredTaken] = predicted_taken;
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}
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/** Returns whether the instruction mispredicted. */
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bool mispredicted()
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{
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TheISA::PCState tempPC = pc;
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TheISA::advancePC(tempPC, staticInst);
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return !(tempPC == predPC);
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}
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//
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// Instruction types. Forward checks to StaticInst object.
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//
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bool isNop() const { return staticInst->isNop(); }
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bool isMemRef() const { return staticInst->isMemRef(); }
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bool isLoad() const { return staticInst->isLoad(); }
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bool isStore() const { return staticInst->isStore(); }
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bool isStoreConditional() const
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{ return staticInst->isStoreConditional(); }
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bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
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bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
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bool isInteger() const { return staticInst->isInteger(); }
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bool isFloating() const { return staticInst->isFloating(); }
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bool isControl() const { return staticInst->isControl(); }
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bool isCall() const { return staticInst->isCall(); }
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bool isReturn() const { return staticInst->isReturn(); }
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bool isDirectCtrl() const { return staticInst->isDirectCtrl(); }
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bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
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bool isCondCtrl() const { return staticInst->isCondCtrl(); }
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bool isUncondCtrl() const { return staticInst->isUncondCtrl(); }
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bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
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bool isThreadSync() const { return staticInst->isThreadSync(); }
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bool isSerializing() const { return staticInst->isSerializing(); }
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bool isSerializeBefore() const
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{ return staticInst->isSerializeBefore() || status[SerializeBefore]; }
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bool isSerializeAfter() const
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{ return staticInst->isSerializeAfter() || status[SerializeAfter]; }
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bool isSquashAfter() const { return staticInst->isSquashAfter(); }
|
|
bool isMemBarrier() const { return staticInst->isMemBarrier(); }
|
|
bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
|
|
bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
|
|
bool isQuiesce() const { return staticInst->isQuiesce(); }
|
|
bool isIprAccess() const { return staticInst->isIprAccess(); }
|
|
bool isUnverifiable() const { return staticInst->isUnverifiable(); }
|
|
bool isSyscall() const { return staticInst->isSyscall(); }
|
|
bool isMacroop() const { return staticInst->isMacroop(); }
|
|
bool isMicroop() const { return staticInst->isMicroop(); }
|
|
bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
|
|
bool isLastMicroop() const { return staticInst->isLastMicroop(); }
|
|
bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
|
|
bool isMicroBranch() const { return staticInst->isMicroBranch(); }
|
|
|
|
/** Temporarily sets this instruction as a serialize before instruction. */
|
|
void setSerializeBefore() { status.set(SerializeBefore); }
|
|
|
|
/** Clears the serializeBefore part of this instruction. */
|
|
void clearSerializeBefore() { status.reset(SerializeBefore); }
|
|
|
|
/** Checks if this serializeBefore is only temporarily set. */
|
|
bool isTempSerializeBefore() { return status[SerializeBefore]; }
|
|
|
|
/** Temporarily sets this instruction as a serialize after instruction. */
|
|
void setSerializeAfter() { status.set(SerializeAfter); }
|
|
|
|
/** Clears the serializeAfter part of this instruction.*/
|
|
void clearSerializeAfter() { status.reset(SerializeAfter); }
|
|
|
|
/** Checks if this serializeAfter is only temporarily set. */
|
|
bool isTempSerializeAfter() { return status[SerializeAfter]; }
|
|
|
|
/** Sets the serialization part of this instruction as handled. */
|
|
void setSerializeHandled() { status.set(SerializeHandled); }
|
|
|
|
/** Checks if the serialization part of this instruction has been
|
|
* handled. This does not apply to the temporary serializing
|
|
* state; it only applies to this instruction's own permanent
|
|
* serializing state.
|
|
*/
|
|
bool isSerializeHandled() { return status[SerializeHandled]; }
|
|
|
|
/** Returns the opclass of this instruction. */
|
|
OpClass opClass() const { return staticInst->opClass(); }
|
|
|
|
/** Returns the branch target address. */
|
|
TheISA::PCState branchTarget() const
|
|
{ return staticInst->branchTarget(pc); }
|
|
|
|
/** Returns the number of source registers. */
|
|
int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
|
|
|
|
/** Returns the number of destination registers. */
|
|
int8_t numDestRegs() const { return staticInst->numDestRegs(); }
|
|
|
|
// the following are used to track physical register usage
|
|
// for machines with separate int & FP reg files
|
|
int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
|
|
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
|
|
|
|
/** Returns the logical register index of the i'th destination register. */
|
|
RegIndex destRegIdx(int i) const { return staticInst->destRegIdx(i); }
|
|
|
|
/** Returns the logical register index of the i'th source register. */
|
|
RegIndex srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
|
|
|
|
/** Pops a result off the instResult queue */
|
|
template <class T>
|
|
void popResult(T& t)
|
|
{
|
|
if (!instResult.empty()) {
|
|
instResult.front().get(t);
|
|
instResult.pop();
|
|
}
|
|
}
|
|
|
|
/** Read the most recent result stored by this instruction */
|
|
template <class T>
|
|
void readResult(T& t)
|
|
{
|
|
instResult.back().get(t);
|
|
}
|
|
|
|
/** Pushes a result onto the instResult queue */
|
|
template <class T>
|
|
void setResult(T t)
|
|
{
|
|
if (instFlags[RecordResult]) {
|
|
Result instRes;
|
|
instRes.set(t);
|
|
instResult.push(instRes);
|
|
}
|
|
}
|
|
|
|
/** Records an integer register being set to a value. */
|
|
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
|
|
{
|
|
setResult<uint64_t>(val);
|
|
}
|
|
|
|
/** Records an fp register being set to a value. */
|
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
|
|
int width)
|
|
{
|
|
if (width == 32 || width == 64) {
|
|
setResult<double>(val);
|
|
} else {
|
|
panic("Unsupported width!");
|
|
}
|
|
}
|
|
|
|
/** Records an fp register being set to a value. */
|
|
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
|
|
{
|
|
setResult<double>(val);
|
|
}
|
|
|
|
/** Records an fp register being set to an integer value. */
|
|
void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
|
|
int width)
|
|
{
|
|
setResult<uint64_t>(val);
|
|
}
|
|
|
|
/** Records an fp register being set to an integer value. */
|
|
void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
|
|
{
|
|
setResult<uint64_t>(val);
|
|
}
|
|
|
|
/** Records that one of the source registers is ready. */
|
|
void markSrcRegReady();
|
|
|
|
/** Marks a specific register as ready. */
|
|
void markSrcRegReady(RegIndex src_idx);
|
|
|
|
/** Returns if a source register is ready. */
|
|
bool isReadySrcRegIdx(int idx) const
|
|
{
|
|
return this->_readySrcRegIdx[idx];
|
|
}
|
|
|
|
/** Sets this instruction as completed. */
|
|
void setCompleted() { status.set(Completed); }
|
|
|
|
/** Returns whether or not this instruction is completed. */
|
|
bool isCompleted() const { return status[Completed]; }
|
|
|
|
/** Marks the result as ready. */
|
|
void setResultReady() { status.set(ResultReady); }
|
|
|
|
/** Returns whether or not the result is ready. */
|
|
bool isResultReady() const { return status[ResultReady]; }
|
|
|
|
/** Sets this instruction as ready to issue. */
|
|
void setCanIssue() { status.set(CanIssue); }
|
|
|
|
/** Returns whether or not this instruction is ready to issue. */
|
|
bool readyToIssue() const { return status[CanIssue]; }
|
|
|
|
/** Clears this instruction being able to issue. */
|
|
void clearCanIssue() { status.reset(CanIssue); }
|
|
|
|
/** Sets this instruction as issued from the IQ. */
|
|
void setIssued() { status.set(Issued); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isIssued() const { return status[Issued]; }
|
|
|
|
/** Clears this instruction as being issued. */
|
|
void clearIssued() { status.reset(Issued); }
|
|
|
|
/** Sets this instruction as executed. */
|
|
void setExecuted() { status.set(Executed); }
|
|
|
|
/** Returns whether or not this instruction has executed. */
|
|
bool isExecuted() const { return status[Executed]; }
|
|
|
|
/** Sets this instruction as ready to commit. */
|
|
void setCanCommit() { status.set(CanCommit); }
|
|
|
|
/** Clears this instruction as being ready to commit. */
|
|
void clearCanCommit() { status.reset(CanCommit); }
|
|
|
|
/** Returns whether or not this instruction is ready to commit. */
|
|
bool readyToCommit() const { return status[CanCommit]; }
|
|
|
|
void setAtCommit() { status.set(AtCommit); }
|
|
|
|
bool isAtCommit() { return status[AtCommit]; }
|
|
|
|
/** Sets this instruction as committed. */
|
|
void setCommitted() { status.set(Committed); }
|
|
|
|
/** Returns whether or not this instruction is committed. */
|
|
bool isCommitted() const { return status[Committed]; }
|
|
|
|
/** Sets this instruction as squashed. */
|
|
void setSquashed() { status.set(Squashed); }
|
|
|
|
/** Returns whether or not this instruction is squashed. */
|
|
bool isSquashed() const { return status[Squashed]; }
|
|
|
|
//Instruction Queue Entry
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the IQ. */
|
|
void setInIQ() { status.set(IqEntry); }
|
|
|
|
/** Sets this instruction as a entry the IQ. */
|
|
void clearInIQ() { status.reset(IqEntry); }
|
|
|
|
/** Returns whether or not this instruction has issued. */
|
|
bool isInIQ() const { return status[IqEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the IQ. */
|
|
void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);}
|
|
|
|
/** Returns whether or not this instruction is squashed in the IQ. */
|
|
bool isSquashedInIQ() const { return status[SquashedInIQ]; }
|
|
|
|
|
|
//Load / Store Queue Functions
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the LSQ. */
|
|
void setInLSQ() { status.set(LsqEntry); }
|
|
|
|
/** Sets this instruction as a entry the LSQ. */
|
|
void removeInLSQ() { status.reset(LsqEntry); }
|
|
|
|
/** Returns whether or not this instruction is in the LSQ. */
|
|
bool isInLSQ() const { return status[LsqEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the LSQ. */
|
|
void setSquashedInLSQ() { status.set(SquashedInLSQ);}
|
|
|
|
/** Returns whether or not this instruction is squashed in the LSQ. */
|
|
bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
|
|
|
|
|
|
//Reorder Buffer Functions
|
|
//-----------------------
|
|
/** Sets this instruction as a entry the ROB. */
|
|
void setInROB() { status.set(RobEntry); }
|
|
|
|
/** Sets this instruction as a entry the ROB. */
|
|
void clearInROB() { status.reset(RobEntry); }
|
|
|
|
/** Returns whether or not this instruction is in the ROB. */
|
|
bool isInROB() const { return status[RobEntry]; }
|
|
|
|
/** Sets this instruction as squashed in the ROB. */
|
|
void setSquashedInROB() { status.set(SquashedInROB); }
|
|
|
|
/** Returns whether or not this instruction is squashed in the ROB. */
|
|
bool isSquashedInROB() const { return status[SquashedInROB]; }
|
|
|
|
/** Read the PC state of this instruction. */
|
|
const TheISA::PCState pcState() const { return pc; }
|
|
|
|
/** Set the PC state of this instruction. */
|
|
const void pcState(const TheISA::PCState &val) { pc = val; }
|
|
|
|
/** Read the PC of this instruction. */
|
|
const Addr instAddr() const { return pc.instAddr(); }
|
|
|
|
/** Read the PC of the next instruction. */
|
|
const Addr nextInstAddr() const { return pc.nextInstAddr(); }
|
|
|
|
/**Read the micro PC of this instruction. */
|
|
const Addr microPC() const { return pc.microPC(); }
|
|
|
|
bool readPredicate()
|
|
{
|
|
return instFlags[Predicate];
|
|
}
|
|
|
|
void setPredicate(bool val)
|
|
{
|
|
instFlags[Predicate] = val;
|
|
|
|
if (traceData) {
|
|
traceData->setPredicate(val);
|
|
}
|
|
}
|
|
|
|
/** Sets the ASID. */
|
|
void setASID(short addr_space_id) { asid = addr_space_id; }
|
|
|
|
/** Sets the thread id. */
|
|
void setTid(ThreadID tid) { threadNumber = tid; }
|
|
|
|
/** Sets the pointer to the thread state. */
|
|
void setThreadState(ImplState *state) { thread = state; }
|
|
|
|
/** Returns the thread context. */
|
|
ThreadContext *tcBase() { return thread->getTC(); }
|
|
|
|
public:
|
|
/** Sets the effective address. */
|
|
void setEA(Addr &ea) { instEffAddr = ea; instFlags[EACalcDone] = true; }
|
|
|
|
/** Returns the effective address. */
|
|
const Addr &getEA() const { return instEffAddr; }
|
|
|
|
/** Returns whether or not the eff. addr. calculation has been completed. */
|
|
bool doneEACalc() { return instFlags[EACalcDone]; }
|
|
|
|
/** Returns whether or not the eff. addr. source registers are ready. */
|
|
bool eaSrcsReady();
|
|
|
|
/** Is this instruction's memory access uncacheable. */
|
|
bool uncacheable() { return instFlags[IsUncacheable]; }
|
|
|
|
/** Has this instruction generated a memory request. */
|
|
bool hasRequest() { return instFlags[ReqMade]; }
|
|
|
|
/** Returns iterator to this instruction in the list of all insts. */
|
|
ListIt &getInstListIt() { return instListIt; }
|
|
|
|
/** Sets iterator for this instruction in the list of all insts. */
|
|
void setInstListIt(ListIt _instListIt) { instListIt = _instListIt; }
|
|
|
|
public:
|
|
/** Returns the number of consecutive store conditional failures. */
|
|
unsigned readStCondFailures()
|
|
{ return thread->storeCondFailures; }
|
|
|
|
/** Sets the number of consecutive store conditional failures. */
|
|
void setStCondFailures(unsigned sc_failures)
|
|
{ thread->storeCondFailures = sc_failures; }
|
|
};
|
|
|
|
template<class Impl>
|
|
Fault
|
|
BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
|
|
unsigned size, unsigned flags)
|
|
{
|
|
instFlags[ReqMade] = true;
|
|
Request *req = NULL;
|
|
Request *sreqLow = NULL;
|
|
Request *sreqHigh = NULL;
|
|
|
|
if (instFlags[ReqMade] && translationStarted()) {
|
|
req = savedReq;
|
|
sreqLow = savedSreqLow;
|
|
sreqHigh = savedSreqHigh;
|
|
} else {
|
|
req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
|
|
thread->contextId(), threadNumber);
|
|
|
|
// Only split the request if the ISA supports unaligned accesses.
|
|
if (TheISA::HasUnalignedMemAcc) {
|
|
splitRequest(req, sreqLow, sreqHigh);
|
|
}
|
|
initiateTranslation(req, sreqLow, sreqHigh, NULL, BaseTLB::Read);
|
|
}
|
|
|
|
if (translationCompleted()) {
|
|
if (fault == NoFault) {
|
|
effAddr = req->getVaddr();
|
|
effSize = size;
|
|
instFlags[EffAddrValid] = true;
|
|
|
|
if (cpu->checker) {
|
|
if (reqToVerify != NULL) {
|
|
delete reqToVerify;
|
|
}
|
|
reqToVerify = new Request(*req);
|
|
}
|
|
fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
|
|
} else {
|
|
// Commit will have to clean up whatever happened. Set this
|
|
// instruction as executed.
|
|
this->setExecuted();
|
|
}
|
|
|
|
if (fault != NoFault) {
|
|
// Return a fixed value to keep simulation deterministic even
|
|
// along misspeculated paths.
|
|
if (data)
|
|
bzero(data, size);
|
|
}
|
|
}
|
|
|
|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
template<class Impl>
|
|
Fault
|
|
BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
|
|
Addr addr, unsigned flags, uint64_t *res)
|
|
{
|
|
if (traceData) {
|
|
traceData->setAddr(addr);
|
|
}
|
|
|
|
instFlags[ReqMade] = true;
|
|
Request *req = NULL;
|
|
Request *sreqLow = NULL;
|
|
Request *sreqHigh = NULL;
|
|
|
|
if (instFlags[ReqMade] && translationStarted()) {
|
|
req = savedReq;
|
|
sreqLow = savedSreqLow;
|
|
sreqHigh = savedSreqHigh;
|
|
} else {
|
|
req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(),
|
|
thread->contextId(), threadNumber);
|
|
|
|
// Only split the request if the ISA supports unaligned accesses.
|
|
if (TheISA::HasUnalignedMemAcc) {
|
|
splitRequest(req, sreqLow, sreqHigh);
|
|
}
|
|
initiateTranslation(req, sreqLow, sreqHigh, res, BaseTLB::Write);
|
|
}
|
|
|
|
if (fault == NoFault && translationCompleted()) {
|
|
effAddr = req->getVaddr();
|
|
effSize = size;
|
|
instFlags[EffAddrValid] = true;
|
|
|
|
if (cpu->checker) {
|
|
if (reqToVerify != NULL) {
|
|
delete reqToVerify;
|
|
}
|
|
reqToVerify = new Request(*req);
|
|
}
|
|
fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
|
|
}
|
|
|
|
return fault;
|
|
}
|
|
|
|
template<class Impl>
|
|
inline void
|
|
BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
|
|
RequestPtr &sreqHigh)
|
|
{
|
|
// Check to see if the request crosses the next level block boundary.
|
|
unsigned block_size = cpu->getDataPort().peerBlockSize();
|
|
Addr addr = req->getVaddr();
|
|
Addr split_addr = roundDown(addr + req->getSize() - 1, block_size);
|
|
assert(split_addr <= addr || split_addr - addr < block_size);
|
|
|
|
// Spans two blocks.
|
|
if (split_addr > addr) {
|
|
req->splitOnVaddr(split_addr, sreqLow, sreqHigh);
|
|
}
|
|
}
|
|
|
|
template<class Impl>
|
|
inline void
|
|
BaseDynInst<Impl>::initiateTranslation(RequestPtr req, RequestPtr sreqLow,
|
|
RequestPtr sreqHigh, uint64_t *res,
|
|
BaseTLB::Mode mode)
|
|
{
|
|
translationStarted(true);
|
|
|
|
if (!TheISA::HasUnalignedMemAcc || sreqLow == NULL) {
|
|
WholeTranslationState *state =
|
|
new WholeTranslationState(req, NULL, res, mode);
|
|
|
|
// One translation if the request isn't split.
|
|
DataTranslation<BaseDynInstPtr> *trans =
|
|
new DataTranslation<BaseDynInstPtr>(this, state);
|
|
cpu->dtb->translateTiming(req, thread->getTC(), trans, mode);
|
|
if (!translationCompleted()) {
|
|
// Save memory requests.
|
|
savedReq = state->mainReq;
|
|
savedSreqLow = state->sreqLow;
|
|
savedSreqHigh = state->sreqHigh;
|
|
}
|
|
} else {
|
|
WholeTranslationState *state =
|
|
new WholeTranslationState(req, sreqLow, sreqHigh, NULL, res, mode);
|
|
|
|
// Two translations when the request is split.
|
|
DataTranslation<BaseDynInstPtr> *stransLow =
|
|
new DataTranslation<BaseDynInstPtr>(this, state, 0);
|
|
DataTranslation<BaseDynInstPtr> *stransHigh =
|
|
new DataTranslation<BaseDynInstPtr>(this, state, 1);
|
|
|
|
cpu->dtb->translateTiming(sreqLow, thread->getTC(), stransLow, mode);
|
|
cpu->dtb->translateTiming(sreqHigh, thread->getTC(), stransHigh, mode);
|
|
if (!translationCompleted()) {
|
|
// Save memory requests.
|
|
savedReq = state->mainReq;
|
|
savedSreqLow = state->sreqLow;
|
|
savedSreqHigh = state->sreqHigh;
|
|
}
|
|
}
|
|
}
|
|
|
|
template<class Impl>
|
|
inline void
|
|
BaseDynInst<Impl>::finishTranslation(WholeTranslationState *state)
|
|
{
|
|
fault = state->getFault();
|
|
|
|
instFlags[IsUncacheable] = state->isUncacheable();
|
|
|
|
if (fault == NoFault) {
|
|
physEffAddr = state->getPaddr();
|
|
memReqFlags = state->getFlags();
|
|
|
|
if (state->mainReq->isCondSwap()) {
|
|
assert(state->res);
|
|
state->mainReq->setExtraData(*state->res);
|
|
}
|
|
|
|
} else {
|
|
state->deleteReqs();
|
|
}
|
|
delete state;
|
|
|
|
translationCompleted(true);
|
|
}
|
|
|
|
#endif // __CPU_BASE_DYN_INST_HH__
|