Ron Dreslinski 31fc398f06 Fixes so that it compiles properly. Still working on .py file issues. ... SConscript: Add Back memory to be built mem/physical.hh: Fix function declerations python/m5/objects/BaseCPU.py: Remove IL1 and DL1 params from the cpu object --HG-- extra : convert_revision : 2f285dc626bc8d84d095def68e986fe7e6f3d8e9		2006-02-27 16:33:11 -05:00
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bus.hh	Rename Port address range functions... like the block size	2006-02-21 12:32:45 -05:00
mem_object.hh	Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system.	2006-02-15 14:21:09 -05:00
packet.hh	Many changes that make the new mem system compile. Now to convert the rest of the tree to use the new mem system.	2006-02-15 14:21:09 -05:00
page_table.cc	Revert PageTable code back to non-asid version.	2006-02-20 20:53:38 -05:00
page_table.hh	Revert PageTable code back to non-asid version.	2006-02-20 20:53:38 -05:00
physical.cc	Add support for multiple ports on the memory. Hook up simple cpu to memory.	2006-02-23 17:02:34 -05:00
physical.hh	Fixes so that it compiles properly. Still working on .py file issues.	2006-02-27 16:33:11 -05:00
port.cc	Update functional memory to have a response event	2006-02-23 13:51:54 -05:00
port.hh	Some more changes for compilation. Since memset is now part of port and not virtual, no need for memory to define them.	2006-02-21 20:04:23 -05:00
request.hh	More progress toward compiling... partly by	2006-02-15 17:52:49 -05:00
translating_port.cc	Some more changes for compilation. Since memset is now part of port and not virtual, no need for memory to define them.	2006-02-21 20:04:23 -05:00
translating_port.hh	Some more changes for compilation. Since memset is now part of port and not virtual, no need for memory to define them.	2006-02-21 20:04:23 -05:00