gem5/cpu/o3/alpha_dyn_inst.hh
Gabe Black 8e4ec55703 Changed the floating point register file into a class with appropriate accessor functions. The width of the floating point register to access can be specified, and if not, it will be accessed at its "natural" width. That is, the width of each individual register. Also, the functions which access the bit representation of floating point registers can use the blahblahBits functions now instead of blahblahInt.
arch/alpha/arguments.cc:
    Renamed readFloatRegInt to readFloatRegBits
arch/alpha/ev5.cc:
    Removed the Double from setFloatRegDouble
arch/alpha/registerfile.hh:
    Changed the floating point register file from a union of arrays to a class with appropriate accessor functions. The interface is necessary for SPARC.
arch/alpha/types.hh:
    Changed the FloatReg type from a union of uint64_t and double to a double, and defined a new type FloatRegBits which is a uint64_t and is used to return the bits which compose a floating point register rather than the value of the register.
arch/isa_parser.py:
    Adjusted the makeRead and makeWrite functions to generate the new versions of readFloatReg and setFloatReg.
base/remote_gdb.cc:
kern/tru64/tru64.hh:
    Replaced setFloatRegInt with setFloatRegBits
cpu/cpu_exec_context.cc:
    Removed the duplicated code for setting the floating point registers, and renamed the function to setFloatRegBits and readFloatRegBits.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/o3/alpha_cpu_impl.hh:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/cpu.cc:
cpu/o3/cpu.hh:
cpu/o3/regfile.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.hh:
    Implemented the new versions of the floating point read and set functions.
cpu/simple/cpu.cc:
    Replaced setFloatRegDouble with setFloatReg

--HG--
extra : convert_revision : 3dad06224723137f6033c335fb8f6395636767f2
2006-03-14 15:55:00 -05:00

264 lines
8.3 KiB
C++

/*
* Copyright (c) 2004-2005 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __CPU_O3_CPU_ALPHA_DYN_INST_HH__
#define __CPU_O3_CPU_ALPHA_DYN_INST_HH__
#include "cpu/base_dyn_inst.hh"
#include "cpu/o3/alpha_cpu.hh"
#include "cpu/o3/alpha_impl.hh"
#include "cpu/inst_seq.hh"
/**
* Mostly implementation specific AlphaDynInst. It is templated in case there
* are other implementations that are similar enough to be able to use this
* class without changes. This is mainly useful if there are multiple similar
* CPU implementations of the same ISA.
*/
template <class Impl>
class AlphaDynInst : public BaseDynInst<Impl>
{
public:
/** Typedef for the CPU. */
typedef typename Impl::FullCPU FullCPU;
/** Binary machine instruction type. */
typedef TheISA::MachInst MachInst;
/** Logical register index type. */
typedef TheISA::RegIndex RegIndex;
/** Integer register index type. */
typedef TheISA::IntReg IntReg;
/** Misc register index type. */
typedef TheISA::MiscReg MiscReg;
enum {
MaxInstSrcRegs = TheISA::MaxInstSrcRegs, //< Max source regs
MaxInstDestRegs = TheISA::MaxInstDestRegs, //< Max dest regs
};
public:
/** BaseDynInst constructor given a binary instruction. */
AlphaDynInst(MachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
FullCPU *cpu);
/** BaseDynInst constructor given a static inst pointer. */
AlphaDynInst(StaticInstPtr &_staticInst);
/** Executes the instruction.*/
Fault execute()
{
return this->fault = this->staticInst->execute(this, this->traceData);
}
public:
MiscReg readMiscReg(int misc_reg)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return 0;
}
MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return 0;
}
Fault setMiscReg(int misc_reg, const MiscReg &val)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return NoFault;
}
Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
{
// Dummy function for now.
// @todo: Fix this once reg file gets fixed.
return NoFault;
}
#if FULL_SYSTEM
Fault hwrei();
int readIntrFlag();
void setIntrFlag(int val);
bool inPalMode();
void trap(Fault fault);
bool simPalCheck(int palFunc);
#else
void syscall();
#endif
private:
/** Physical register index of the destination registers of this
* instruction.
*/
PhysRegIndex _destRegIdx[MaxInstDestRegs];
/** Physical register index of the source registers of this
* instruction.
*/
PhysRegIndex _srcRegIdx[MaxInstSrcRegs];
/** Physical register index of the previous producers of the
* architected destinations.
*/
PhysRegIndex _prevDestRegIdx[MaxInstDestRegs];
public:
// The register accessor methods provide the index of the
// instruction's operand (e.g., 0 or 1), not the architectural
// register index, to simplify the implementation of register
// renaming. We find the architectural register index by indexing
// into the instruction's own operand index table. Note that a
// raw pointer to the StaticInst is provided instead of a
// ref-counted StaticInstPtr to redice overhead. This is fine as
// long as these methods don't copy the pointer into any long-term
// storage (which is pretty hard to imagine they would have reason
// to do).
uint64_t readIntReg(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
FloatReg readFloatReg(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
FloatReg readFloatReg(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
void setIntReg(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
this->instResult.integer = val;
}
void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
this->instResult.fp = val;
}
void setFloatReg(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
this->instResult.dbl = val;
}
void setFloatRegBits(const StaticInst *si, int idx,
FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
this->instResult.integer = val;
}
void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
this->instResult.integer = val;
}
/** Returns the physical register index of the i'th destination
* register.
*/
PhysRegIndex renamedDestRegIdx(int idx) const
{
return _destRegIdx[idx];
}
/** Returns the physical register index of the i'th source register. */
PhysRegIndex renamedSrcRegIdx(int idx) const
{
return _srcRegIdx[idx];
}
/** Returns the physical register index of the previous physical register
* that remapped to the same logical register index.
*/
PhysRegIndex prevDestRegIdx(int idx) const
{
return _prevDestRegIdx[idx];
}
/** Renames a destination register to a physical register. Also records
* the previous physical register that the logical register mapped to.
*/
void renameDestReg(int idx,
PhysRegIndex renamed_dest,
PhysRegIndex previous_rename)
{
_destRegIdx[idx] = renamed_dest;
_prevDestRegIdx[idx] = previous_rename;
}
/** Renames a source logical register to the physical register which
* has/will produce that logical register's result.
* @todo: add in whether or not the source register is ready.
*/
void renameSrcReg(int idx, PhysRegIndex renamed_src)
{
_srcRegIdx[idx] = renamed_src;
}
public:
Fault calcEA()
{
return this->staticInst->eaCompInst()->execute(this, this->traceData);
}
Fault memAccess()
{
return this->staticInst->memAccInst()->execute(this, this->traceData);
}
};
#endif // __CPU_O3_CPU_ALPHA_DYN_INST_HH__